Datasheet AD9375 (Analog Devices) - 5

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Data Sheet AD9375 Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Carrier Leakage After calibration, LOL correction active, CW7 input signal, 3 dB RF and 3 dB digital attenuation, 40 kHz measurement BW 700 MHz LO −81 dBFS6 2600 MHz LO −81 dBFS6 3500 MHz LO −81 dBFS6 5500 MHz LO −75 dBFS6 Error Vector Magnitude (3GPP EVM Long-term evolution (LTE) Test Signals) 20 MHz downlink, 5 dB RF attenuation 700 MHz LO −45 dB 2600 MHz LO −39 dB 3500 MHz LO −38.5 dB 5500 MHz LO −37.5 dB Output Impedance 50 Ω Differential RECEIVERS (Rx) Center Frequency 300 6000 MHz Gain Range 0 30 dB Analog Gain Step 0.5 dB BW Ripple ±0.5 dB 100 MHz BW, compensated by programmable FIR filter ±0.2 dB Any 20 MHz span, compensated by programmable FIR filter Rx Bandwidth 8 100 MHz Analog low-pass filter (LPF) BW is 20 MHz minimum, programmable FIR BW configurable over the entire range Rx Alias Band Rejection 75 dB Due to digital filters Maximum Recommended Input −14 dBm Input is a CW7 signal at a 0 dB Power8 attenuation setting; this level increases decibel for decibel with attenuation Noise Figure NF Maximum Rx gain, at Rx port, matching losses de-embedded 700 MHz LO 12 dB 2600 MHz LO 13.5 dB 3500 MHz LO 14 dB 5500 MHz LO 18 dB Input Third-Order Intercept Point IIP3 Maximum Rx gain, third- order intermodulation (IM3) 1 MHz offset from LO 700 MHz LO 22 dBm 2600 MHz LO 22 dBm 3500 MHz LO 20 dBm 5500 MHz LO 20 dBm Input Second-Order Intercept IIP2 Maximum Rx gain, second- Point order intermodulation (IM2) 1 MHz offset from LO 700 MHz LO 65 dBm 2600 MHz LO 65 dBm 3500 MHz LO 65 dBm 5500 MHz LO 57 dBm Rev. 0 | Page 5 of 61 Document Outline Features Applications General Description Revision History Functional Block Diagram Specifications Current and Power Consumption Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Reflow Profile Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics 700 MHz Band 2.6 GHz Band 3.5 GHz Band 5.5 GHz Band Theory of Operation Transmitter (Tx) Receiver (Rx) Observation Receiver (ORx) Sniffer Receiver (SnRx) Clock Input Synthesizers RF PLL Clock PLL Serial Peripheral Interface (SPI) GPIO_x AND GPIO_3P3_x Pins Auxiliary Converters Auxiliary ADC Inputs (AUXADC_x) Auxiliary DACs (AUXDAC_x) JESD204B Data Interface Power Supply Sequence Digital Predistortion (DPD) JTAG Boundary Scan Outline Dimensions Ordering Guide