Datasheet ADRV9008-1 (Analog Devices) - 8

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ADRV9008-1 Data Sheet Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Bus Turnaround Time, Read t 0 t ns HZS CO After ADRV9008-1 Drives Last Data Bit JESD204B DATA OUTPUT AC-coupled TIMING Unit Interval UI 81.38 320 ps Data Rate Per Channel (NRZ) 3125 12288 Mbps Rise Time t 24 39.5 ps 20% to 80% in 100 Ω load R Fall Time t 24 39.4 ps 20% to 80% in 100 Ω load F Output Common-Mode V 0 1.8 V AC-coupled CM Voltage Differential Output Voltage V 360 600 770 mV DIFF Short-Circuit Current I −100 +100 mA DSHORT Differential Termination 80 94.2 120 Ω Impedance Total Jitter 15.13 ps Bit error rate (BER) = 10−15 Uncorrelated Bounded UBHPJ 0.56 ps High Probability Jitter Duty Cycle Distortion DCD 0.369 ps SYSREF_IN± Setup Time to 2.5 ns See Figure 2 REF_CLK_IN± SYSREF_IN± Hold Time to −1.5 ns See Figure 2 REF_CLK_IN± Latency t REF_CLK_IN± = 245.76 MHz LAT_FRM 89.4 Clock Receiver bandwidth = 200 MHz, IQ rate = cycles 245.76 MHz, lane rate = 9830.4 MHz, M = 2, L = 2, N = 16, S = 1 364.18 ns 1 VDDA1P3 refers to all analog 1.3 V supplies, including VDDA1P3_RF_SYNTH, VDDA1P3_BB, VDDA1P3_RX_RF, VDDA1P3_RF_VCO_LDO, VDDA1P3_RF_LO, VDDA1P3_SER, VDDA1P3_CLOCK_SYNTH, VDDA1P3_CLOCK_VCO_LDO, VDDA1P3_AUX_SYNTH, and VDDA1P3_AUX_VCO_LDO.
CURRENT AND POWER CONSUMPTION SPECIFICATIONS Table 2. Parameter Min Typ Max Unit Test Conditions/Comments
SUPPLY CHARACTERISTICS VDDA1P31 Analog Supply 1.267 1.3 1.33 V VDDD1P3_DIG Supply 1.267 1.3 1.33 V VDDA1P8_AN Supply 1.71 1.8 1.89 V VDDA1P8_BB Supply 1.71 1.8 1.89 V VDD_INTERFACE Supply 1.71 1.8 2.625 V CMOS and LVDS supply, 1.8 V to 2.5 V nominal range VDDA_3P3 Supply 3.135 3.3 3.465 V POSITIVE SUPPLY CURRENT LO at 2600 MHz 200 MHz Receiver Bandwidth Two receivers enabled VDDA1P31 Analog Supply 1645 mA VDDD1P3_DIG Supply 984 mA Receiver QEC active VDDA1P8_AN Supply 0.4 mA VDDA1P8_BB Supply 68 mA VDD_INTERFACE Supply 8 mA VDDA_3P3 Supply 3 mA No Auxiliary DAC x or AUXADC_x enabled (if enabled, AUXADC_x adds 2.7 mA, and each Auxiliary DAC x adds 1.5 mA) Total Power Dissipation 3.57 W Typical supply voltages, receiver QEC active 1 VDDA1P3 refers to all analog 1.3 V supplies, including VDDA1P3_RF_SYNTH, VDDA1P3_BB, VDDA1P3_RX_RF, VDDA1P3_RX, VDDA1P3_RF_VCO_LDO, VDDA1P3_RF_LO, VDDA1P3_SER, VDDA1P3_CLOCK_SYNTH, VDDA1P3_CLOCK_VCO_LDO, VDDA1P3_AUX_SYNTH, and VDDA1P3_AUX_VCO_LDO. Rev. 0 | Page 8 of 68 Document Outline Features Applications General Description Revision History Functional Block Diagram Specifications Current and Power Consumption Specifications Timing Diagrams Absolute Maximum Ratings Reflow Profile Thermal Management Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics 75 MHz to 525 MHz Band 650 MHz to 3000 MHz Band 3400 MHz to 4800 MHz Band 5100 MHz to 5900 MHz Band Receiver Input Impedance Terminology Theory of Operation Receivers Clock Input Synthesizers RF PLL Clock PLL SPI JTAG Boundary Scan Power Supply Sequence GPIO_x Pins Auxiliary Converters AUXADC_x Auxiliary DAC x JESD204B Data Interface Applications Information PCB Layout and Power Supply Recommendations Overview PCB Material and Stackup Selection Fanout and Trace Space Guidelines Component Placement and Routing Guidelines Signals with Highest Routing Priority Signals with Second Routing Priority Signals with Lowest Routing Priority RF and JESD204B Transmission Line Layout RF Routing Guidelines JESD204B Trace Routing Recommendations Routing Recommendations Stripline Transmission Lines vs. Microstrip Transmission Lines Isolation Techniques Used on the ADRV9008-1W/PCBZ Isolation Goals Isolation Between JESD204B Lines RF Port Interface Information RF Port Impedance Data Advanced Design System (ADS) Setup Using the DataAccessComponent and SEDZ File General Receiver Path Interface Impedance Matching Network Examples Outline Dimensions Ordering Guide