Datasheet ADRV9008-1 (Analog Devices) - 5

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Data Sheet ADRV9008-1 Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Second-Order Input IIP2 62 dBm 75 MHz < f ≤ 600 MHz, (P − 12) dB per HIGH Intermodulation tone; 600 MHz < f ≤ 6000 MHz, (P − 10) dB HIGH Intercept Point per tone; 0 dB attenuation, complex Image Rejection 75 dB QEC active, within 200 MHz receiver bandwidth Input Impedance 100 Ω Differential (see Figure 168) Receiver to Receiver 77 dB 75 MHz < f ≤ 600 MHz Isolation 65 dB 600 MHz < f ≤ 4800 MHz 61 dB 4800 MHz < f ≤ 6000 MHz Receiver Band Spurs −95 dBm No more than one spur at this level per Referenced to RF Input at 10 MHz of receiver bandwidth Maximum Gain Receiver LO Leakage at Leakage decreases decibel for decibel with Receiver Input at attenuation for first 12 dB Maximum Gain −70 dBm 75 MHz < f ≤ 600 MHz −70 dBm 600 MHz < f ≤ 3000 MHz −65 dBm 3000 MHz < f ≤ 6000 MHz LO SYNTHESIZER LO Frequency Step 2.3 Hz 1.5 GHz to 2.8 GHz, 76.8 MHz phase frequency detector (PFD) frequency LO Spur −85 dBc Excludes integer boundary spurs Integrated Phase Noise 2 kHz to 18 MHz 75 MHz LO 0.014 °rms Narrow PLL loop bandwidth (50 kHz) 1900 MHz LO 0.2 °rms Narrow PLL loop bandwidth (50 kHz) 3800 MHz LO 0.36 °rms Wide PLL loop bandwidth (300 kHz) 5900 MHz LO 0.54 °rms Wide PLL loop bandwidth (300 kHz) Spot Phase Noise 75 MHz LO Narrow PLL loop bandwidth 10 kHz Offset −126.5 dBc/Hz 100 kHz Offset −132.8 dBc/Hz 1 MHz Offset −150.1 dBc/Hz 10 MHz Offset −150.7 dBc/Hz 1900 MHz LO Narrow PLL loop bandwidth 100 kHz Offset −100 dBc/Hz 200 kHz Offset −115 dBc/Hz 400 kHz Offset −120 dBc/Hz 600 kHz Offset −129 dBc/Hz 800 kHz Offset −132 dBc/Hz 1.2 MHz Offset −135 dBc/Hz 1.8 MHz Offset −140 dBc/Hz 6 MHz Offset −150 dBc/Hz 10 MHz Offset −153 dBc/Hz 3800 MHz LO Wide PLL loop bandwidth 100 kHz Offset −104 dBc/Hz 1.2 MHz Offset −125 dBc/Hz 10 MHz Offset −145 dBc/Hz 5900 MHz LO Wide PLL loop bandwidth 100 kHz Offset −99 dBc/Hz 1.2 MHz Offset −119.7 dBc/Hz 10 MHz Offset −135.4 dBc/Hz LO PHASE SYNCHRONIZATION Change in LO delay per temperature change Phase Deviation 1.6 ps/°C Rev. 0 | Page 5 of 68 Document Outline Features Applications General Description Revision History Functional Block Diagram Specifications Current and Power Consumption Specifications Timing Diagrams Absolute Maximum Ratings Reflow Profile Thermal Management Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics 75 MHz to 525 MHz Band 650 MHz to 3000 MHz Band 3400 MHz to 4800 MHz Band 5100 MHz to 5900 MHz Band Receiver Input Impedance Terminology Theory of Operation Receivers Clock Input Synthesizers RF PLL Clock PLL SPI JTAG Boundary Scan Power Supply Sequence GPIO_x Pins Auxiliary Converters AUXADC_x Auxiliary DAC x JESD204B Data Interface Applications Information PCB Layout and Power Supply Recommendations Overview PCB Material and Stackup Selection Fanout and Trace Space Guidelines Component Placement and Routing Guidelines Signals with Highest Routing Priority Signals with Second Routing Priority Signals with Lowest Routing Priority RF and JESD204B Transmission Line Layout RF Routing Guidelines JESD204B Trace Routing Recommendations Routing Recommendations Stripline Transmission Lines vs. Microstrip Transmission Lines Isolation Techniques Used on the ADRV9008-1W/PCBZ Isolation Goals Isolation Between JESD204B Lines RF Port Interface Information RF Port Impedance Data Advanced Design System (ADS) Setup Using the DataAccessComponent and SEDZ File General Receiver Path Interface Impedance Matching Network Examples Outline Dimensions Ordering Guide