Datasheet PIC18F2455, PIC18F2550, PIC18F4455, PIC18F4550 (Microchip) - 3

PIC18F2455/2550/4455/4550 28/40/44-Pin, High-Performance, Enhanced Flash, USB Microcontrollers with nanoWatt Technology Universal Serial Bus Features: Peripheral Highlights:
• USB V2.0 Compliant • High-Current Sink/Source: 25 mA/25 mA • Low Speed (1.5 Mb/s) and Full Speed (12 Mb/s) • Three External Interrupts • Supports Control, Interrupt, Isochronous and Bulk • Four Timer modules (Timer0 to Timer3) Transfers • Up to 2 Capture/Compare/PWM (CCP) modules: • Supports up to 32 Endpoints (16 bidirectional) - Capture is 16-bit, max. resolution 5.2 ns (TCY/16) • 1 Kbyte Dual Access RAM for USB - Compare is 16-bit, max. resolution 83.3 ns (TCY) • On-Chip USB Transceiver with On-Chip Voltage - PWM output: PWM resolution is 1 to 10-bit Regulator • Enhanced Capture/Compare/PWM (ECCP) module: • Interface for Off-Chip USB Transceiver - Multiple output modes • Streaming Parallel Port (SPP) for USB streaming - Selectable polarity transfers (40/44-pin devices only) - Programmable dead time - Auto-shutdown and auto-restart
Power-Managed Modes:
• Enhanced USART module: • Run: CPU on, Peripherals on - LIN bus support • Idle: CPU off, Peripherals on • Master Synchronous Serial Port (MSSP) module • Sleep: CPU off, Peripherals off Supporting 3-Wire SPI (all 4 modes) and I2C™ • Idle mode Currents Down to 5.8 μA Typical Master and Slave modes • Sleep mode Currents Down to 0.1 μA Typical • 10-Bit, Up to 13-Channel Analog-to-Digital Converter • Timer1 Oscil ator: 1.1 μA Typical, 32 kHz, 2V (A/D) module with Programmable Acquisition Time • Watchdog Timer: 2.1 μA Typical • Dual Analog Comparators with Input Multiplexing • Two-Speed Oscil ator Start-up
Special Microcontroller Features: Flexible Oscillator Structure:
• C Compiler Optimized Architecture with Optional • Four Crystal modes, including High-Precision PLL Extended Instruction Set for USB • 100,000 Erase/Write Cycle Enhanced Flash • Two External Clock modes, Up to 48 MHz Program Memory Typical • Internal Oscillator Block: • 1,000,000 Erase/Write Cycle Data EEPROM - 8 user-selectable frequencies, from 31 kHz Memory Typical to 8 MHz • Flash/Data EEPROM Retention: > 40 Years - User-tunable to compensate for frequency drift • Self-Programmable under Software Control • Secondary Oscillator using Timer1 @ 32 kHz • Priority Levels for Interrupts • Dual Oscillator Options allow Microcontroller and • 8 x 8 Single-Cycle Hardware Multiplier USB module to Run at Different Clock Speeds • Extended Watchdog Timer (WDT): • Fail-Safe Clock Monitor: - Programmable period from 41 ms to 131s - Allows for safe shutdown if any clock stops • Programmable Code Protection • Single-Supply 5V In-Circuit Serial Programming™ (ICSP™) via Two Pins • In-Circuit Debug (ICD) via Two Pins • Optional Dedicated ICD/ICSP Port (44-pin, TQFP package only) • Wide Operating Voltage Range (2.0V to 5.5V)
Program Memory Data Memory MSSP s T 10-Bit CCP/ECCP R ator Timers Device I/O SPP ar Flash # Single-Word SRAM EEPROM A/D (ch) (PWM) Master SA 8/16-Bit SPI (bytes) Instructions (bytes) (bytes) I2C™ EU mp Co
PIC18F2455 24K 12288 2048 256 24 10 2/0 No Y Y 1 2 1/3 PIC18F2550 32K 16384 2048 256 24 10 2/0 No Y Y 1 2 1/3 PIC18F4455 24K 12288 2048 256 35 13 1/1 Yes Y Y 1 2 1/3 PIC18F4550 32K 16384 2048 256 35 13 1/1 Yes Y Y 1 2 1/3 © 2009 Microchip Technology Inc. DS39632E-page 1 Document Outline Universal Serial Bus Features: Power-Managed Modes: Flexible Oscillator Structure: Peripheral Highlights: Special Microcontroller Features: Pin Diagrams Pin Diagrams (Continued) Table of Contents Most Current Data Sheet Errata Customer Notification System 1.0 Device Overview 1.1 New Core Features 1.1.1 nanoWatt Technology 1.1.2 Universal Serial Bus (USB) 1.1.3 Multiple Oscillator Options and Features 1.2 Other Special Features 1.3 Details on Individual Family Members TABLE 1-1: Device Features FIGURE 1-1: PIC18F2455/2550 (28-Pin) Block Diagram FIGURE 1-2: PIC18F4455/4550 (40/44-Pin) Block Diagram TABLE 1-2: PIC18f2455/2550 Pinout I/O Descriptions TABLE 1-3: PIC18F4455/4550 Pinout I/O Descriptions 2.0 Oscillator Configurations 2.1 Overview 2.1.1 Oscillator Control 2.2 Oscillator Types 2.2.1 Oscillator Modes and USB Operation FIGURE 2-1: PIC18F2455/2550/4455/4550 Clock Diagram 2.2.2 Crystal Oscillator/Ceramic Resonators FIGURE 2-2: Crystal/Ceramic Resonator Operation (XT, HS or HSPLL Configuration) TABLE 2-1: Capacitor Selection for Ceramic Resonators TABLE 2-2: Capacitor Selection for Crystal Oscillator FIGURE 2-3: External Clock Input Operation (HS Osc Configuration) 2.2.3 External Clock Input FIGURE 2-4: External Clock Input Operation (EC and ECPLL Configuration) FIGURE 2-5: External Clock Input Operation (ECIO and ECPIO Configuration) 2.2.4 PLL Frequency Multiplier FIGURE 2-6: PLL Block Diagram (HS Mode) 2.2.5 Internal Oscillator Block Register 2-1: OSCTUNE: Oscillator Tuning Register 2.3 Oscillator Settings for USB 2.3.1 Low-Speed Operation 2.3.2 Running Different USB and Microcontroller Clocks TABLE 2-3: Oscillator Configuration Options for USB Operation 2.4 Clock Sources and Oscillator Switching 2.4.1 Oscillator Control Register 2.4.2 Oscillator Transitions Register 2-2: OSCCON: Oscillator Control Register 2.5 Effects of Power-Managed Modes on the Various Clock Sources 2.6 Power-up Delays TABLE 2-4: OSC1 and OSC2 Pin States in Sleep Mode 3.0 Power-Managed Modes 3.1 Selecting Power-Managed Modes 3.1.1 Clock Sources 3.1.2 Entering Power-Managed Modes TABLE 3-1: Power-Managed Modes 3.1.3 Clock Transitions and Status Indicators 3.1.4 Multiple Sleep Commands EXAMPLE 3-1: Executing Back to Back SLEEP Instructions 3.2 Run Modes 3.2.1 PRI_RUN Mode 3.2.2 SEC_RUN Mode FIGURE 3-1: Transition Timing for Entry to SEC_RUN Mode FIGURE 3-2: Transition Timing From SEC_RUN Mode to PRI_RUN Mode (HSPLL) 3.2.3 RC_RUN Mode FIGURE 3-3: Transition Timing to RC_RUN Mode FIGURE 3-4: Transition Timing From RC_RUN Mode to PRI_RUN Mode 3.3 Sleep Mode 3.4 Idle Modes FIGURE 3-5: Transition Timing for Entry to Sleep Mode FIGURE 3-6: Transition Timing for Wake From Sleep (HSPLL) 3.4.1 PRI_IDLE Mode 3.4.2 SEC_IDLE Mode FIGURE 3-7: Transition Timing for Entry to Idle Mode FIGURE 3-8: Transition Timing for Wake From Idle to Run Mode 3.4.3 RC_IDLE Mode 3.5 Exiting Idle and Sleep Modes 3.5.1 Exit By Interrupt 3.5.2 Exit By WDT Time-out 3.5.3 Exit By Reset 3.5.4 Exit Without an Oscillator Start-up Delay TABLE 3-2: Exit Delay on Wake-up By Reset From Sleep Mode or Any Idle Mode (By Clock Sources) 4.0 Reset 4.1 RCON Register FIGURE 4-1: Simplified Block Diagram of On-Chip Reset Circuit Register 4-1: RCON: Reset Control Register 4.2 Master Clear Reset (MCLR) 4.3 Power-on Reset (POR) FIGURE 4-2: External Power-on Reset Circuit (for Slow Vdd Power-up) 4.4 Brown-out Reset (BOR) 4.4.1 Software Enabled BOR 4.4.2 Detecting BOR 4.4.3 Disabling BOR in Sleep Mode TABLE 4-1: BOR Configurations 4.5 Device Reset Timers 4.5.1 Power-up Timer (PWRT) 4.5.2 Oscillator Start-up Timer (OST) 4.5.3 PLL Lock Time-out 4.5.4 Time-out Sequence TABLE 4-2: Time-out in Various Situations FIGURE 4-3: Time-out Sequence on Power-up (MCLR Tied to Vdd, Vdd Rise < Tpwrt) FIGURE 4-4: Time-out Sequence on Power-up (MCLR Not Tied to Vdd): Case 1 FIGURE 4-5: Time-out Sequence on Power-up (MCLR Not Tied to Vdd): Case 2 FIGURE 4-6: Slow Rise Time (MCLR Tied to Vdd, Vdd Rise > Tpwrt) FIGURE 4-7: Time-out Sequence on POR w/PLL Enabled (MCLR Tied to Vdd) 4.6 Reset State of Registers TABLE 4-3: Status Bits, Their Significance and the Initialization Condition for RCON Register TABLE 4-4: Initialization Conditions for All Registers 5.0 Memory Organization 5.1 Program Memory Organization FIGURE 5-1: Program Memory Map and Stack 5.1.1 Program Counter 5.1.2 Return Address Stack FIGURE 5-2: Return Address Stack and Associated Registers Register 5-1: STKPTR: Stack Pointer Register 5.1.3 Fast Register Stack EXAMPLE 5-1: Fast Register Stack Code Example 5.1.4 Look-up Tables in Program Memory EXAMPLE 5-2: Computed GOTO Using an Offset Value 5.2 PIC18 Instruction Cycle 5.2.1 Clocking Scheme 5.2.2 Instruction Flow/Pipelining FIGURE 5-3: Clock/ Instruction Cycle EXAMPLE 5-3: Instruction Pipeline Flow 5.2.3 Instructions in Program Memory FIGURE 5-4: Instructions in Program Memory 5.2.4 Two-Word Instructions EXAMPLE 5-4: Two-Word Instructions 5.3 Data Memory Organization 5.3.1 USB RAM 5.3.2 Bank Select Register (BSR) FIGURE 5-5: Data Memory Map FIGURE 5-6: Use of the Bank Select Register (Direct Addressing) 5.3.3 Access Bank 5.3.4 General Purpose Register File 5.3.5 Special Function Registers TABLE 5-1: Special Function Register Map TABLE 5-2: Register File Summary 5.3.6 Status Register Register 5-2: Status Register 5.4 Data Addressing Modes 5.4.1 Inherent and Literal Addressing 5.4.2 Direct Addressing 5.4.3 Indirect Addressing EXAMPLE 5-5: How to Clear RAM (Bank 1) Using Indirect Addressing FIGURE 5-7: Indirect Addressing 5.5 Program Memory and the Extended Instruction Set 5.6 Data Memory and the Extended Instruction Set 5.6.1 Indexed Addressing with Literal Offset 5.6.2 Instructions Affected By Indexed Literal Offset Mode FIGURE 5-8: Comparing Addressing Options for Bit-Oriented and Byte-Oriented Instructions (Extended Instruction Set Enabled) 5.6.3 Mapping the Access Bank in Indexed Literal Offset Mode 5.6.4 BSR in Indexed Literal Offset Mode FIGURE 5-9: Remapping the Access Bank with Indexed Literal Offset Addressing 6.0 Flash Program Memory 6.1 Table Reads and Table Writes FIGURE 6-1: Table Read Operation FIGURE 6-2: Table Write Operation 6.2 Control Registers 6.2.1 EECON1 and EECON2 Registers Register 6-1: EECON1: Data EEPROM Control Register 1 6.2.2 Table Latch Register (TABLAT) 6.2.3 Table Pointer Register (TBLPTR) 6.2.4 Table Pointer Boundaries TABLE 6-1: Table Pointer Operations with TBLRD and TBLWT Instructions FIGURE 6-3: Table Pointer Boundaries Based on Operation 6.3 Reading the Flash Program Memory FIGURE 6-4: Reads From Flash Program Memory EXAMPLE 6-1: Reading a Flash Program Memory Word 6.4 Erasing Flash Program Memory 6.4.1 Flash Program Memory Erase Sequence EXAMPLE 6-2: Erasing a Flash Program Memory Row 6.5 Writing to Flash Program Memory FIGURE 6-5: Table Writes to Flash Program Memory 6.5.1 Flash Program Memory Write Sequence EXAMPLE 6-3: Writing to Flash Program Memory EXAMPLE 6-3: Writing to Flash Program Memory (Continued) 6.5.2 Write Verify 6.5.3 Unexpected Termination of Write Operation 6.5.4 Protection Against Spurious Writes 6.6 Flash Program Operation During Code Protection TABLE 6-2: Registers Associated with Program Flash Memory 7.0 Data EEPROM Memory 7.1 EECON1 and EECON2 Registers Register 7-1: EECON1: Data EEPROM Control Register 1 7.2 Reading the Data EEPROM Memory 7.3 Writing to the Data EEPROM Memory 7.4 Write Verify EXAMPLE 7-1: Data EEPROM Read EXAMPLE 7-2: Data EEPROM Write 7.5 Operation During Code-Protect 7.6 Protection Against Spurious Write 7.7 Using the Data EEPROM EXAMPLE 7-3: Data EEPROM Refresh Routine TABLE 7-1: Registers Associated with Data EEPROM Memory 8.0 8 x 8 Hardware Multiplier 8.1 Introduction 8.2 Operation EXAMPLE 8-1: 8 x 8 Unsigned Multiply Routine EXAMPLE 8-2: 8 x 8 Signed Multiply Routine TABLE 8-1: Performance Comparison for Various Multiply Operations EQUATION 8-1: 16 x 16 Unsigned Multiplication Algorithm EXAMPLE 8-3: 16 x 16 Unsigned Multiply Routine EQUATION 8-2: 16 x 16 Signed Multiplication Algorithm EXAMPLE 8-4: 16 x 16 Signed Multiply Routine 9.0 Interrupts 9.1 USB Interrupts FIGURE 9-1: Interrupt Logic 9.2 INTCON Registers Register 9-1: INTCON: Interrupt Control Register Register 9-2: INTCON2: Interrupt Control Register 2 Register 9-3: INTCON3: Interrupt Control Register 3 9.3 PIR Registers Register 9-4: PIR1: Peripheral Interrupt Request (Flag) Register 1 Register 9-5: PIR2: Peripheral Interrupt Request (Flag) Register 2 9.4 PIE Registers Register 9-6: PIE1: Peripheral Interrupt Enable Register 1 Register 9-7: PIE2: Peripheral Interrupt Enable Register 2 9.5 IPR Registers Register 9-8: IPR1: Peripheral Interrupt Priority Register 1 Register 9-9: IPR2: Peripheral Interrupt Priority Register 2 9.6 RCON Register Register 9-10: RCON: Reset Control Register 9.7 INTx Pin Interrupts 9.8 TMR0 Interrupt 9.9 PORTB Interrupt-on-Change 9.10 Context Saving During Interrupts EXAMPLE 9-1: Saving Status, WREG and BSR Registers in RAM 10.0 I/O Ports FIGURE 10-1: Generic I/O Port Operation 10.1 PORTA, TRISA and LATA Registers EXAMPLE 10-1: Initializing PORTA TABLE 10-1: PORTA I/O Summary TABLE 10-2: Summary of Registers Associated with PORTA 10.2 PORTB, TRISB and LATB Registers EXAMPLE 10-2: Initializing PORTB TABLE 10-3: PORTB I/O Summary TABLE 10-4: Summary of Registers Associated with PORTB 10.3 PORTC, TRISC and LATC Registers EXAMPLE 10-3: Initializing PORTC TABLE 10-5: PORTC I/O Summary TABLE 10-6: Summary of Registers Associated with PORTC 10.4 PORTD, TRISD and LATD Registers EXAMPLE 10-4: Initializing PORTD TABLE 10-7: PORTD I/O Summary TABLE 10-8: Summary of Registers Associated with PORTD 10.5 PORTE, TRISE and LATE Registers EXAMPLE 10-5: Initializing PORTE 10.5.1 PORTE in 28-Pin Devices Register 10-1: PORTE Register TABLE 10-9: PORTE I/O Summary TABLE 10-10: Summary of Registers Associated with PORTE 11.0 Timer0 Module Register 11-1: T0CON: Timer0 Control Register 11.1 Timer0 Operation 11.2 Timer0 Reads and Writes in 16-Bit Mode FIGURE 11-1: Timer0 Block Diagram (8-bit Mode) FIGURE 11-2: Timer0 Block Diagram (16-bit Mode) 11.3 Prescaler 11.3.1 Switching Prescaler Assignment 11.4 Timer0 Interrupt TABLE 11-1: Registers Associated with Timer0 12.0 Timer1 Module Register 12-1: T1CON: Timer1 Control Register 12.1 Timer1 Operation FIGURE 12-1: Timer1 Block Diagram FIGURE 12-2: Timer1 Block Diagram (16-bit Read/Write Mode) 12.2 Timer1 16-Bit Read/Write Mode 12.3 Timer1 Oscillator FIGURE 12-3: External Components for the Timer1 LP Oscillator TABLE 12-1: Capacitor Selection for the Timer Oscillator(2,3,4) 12.3.1 Using Timer1 as a Clock Source 12.3.2 Low-Power Timer1 Option 12.3.3 Timer1 Oscillator Layout Considerations FIGURE 12-4: Oscillator Circuit with Grounded Guard Ring 12.4 Timer1 Interrupt 12.5 Resetting Timer1 Using the CCP Special Event Trigger 12.6 Using Timer1 as a Real-Time Clock 12.7 Considerations in Asynchronous Counter Mode EXAMPLE 12-1: Implementing a Real-Time Clock Using a Timer1 Interrupt Service TABLE 12-2: Registers Associated with Timer1 as a Timer/Counter 13.0 Timer2 Module 13.1 Timer2 Operation Register 13-1: T2CON: Timer2 Control Register 13.2 Timer2 Interrupt 13.3 TMR2 Output FIGURE 13-1: Timer2 Block Diagram TABLE 13-1: Registers Associated with Timer2 as a Timer/Counter 14.0 Timer3 Module Register 14-1: T3CON: Timer3 Control Register 14.1 Timer3 Operation FIGURE 14-1: Timer3 Block Diagram FIGURE 14-2: Timer3 Block Diagram (16-bit Read/Write Mode) 14.2 Timer3 16-Bit Read/Write Mode 14.3 Using the Timer1 Oscillator as the Timer3 Clock Source 14.4 Timer3 Interrupt 14.5 Resetting Timer3 Using the CCP Special Event Trigger TABLE 14-1: Registers Associated with Timer3 as a Timer/Counter 15.0 Capture/Compare/PWM (CCP) Modules Register 15-1: CCPxCON: Standard CCPx Control Register 15.1 CCP Module Configuration 15.1.1 CCP Modules and Timer Resources TABLE 15-1: CCP Mode – Timer Resource 15.1.2 CCP2 Pin Assignment TABLE 15-2: Interactions Between CCP1 and CCP2 for Timer Resources 15.2 Capture Mode 15.2.1 CCP Pin Configuration 15.2.2 Timer1/Timer3 Mode Selection 15.2.3 Software Interrupt 15.2.4 CCP Prescaler EXAMPLE 15-1: Changing Between Capture Prescalers (CCP2 Shown) FIGURE 15-1: Capture Mode Operation Block Diagram 15.3 Compare Mode 15.3.1 CCP Pin Configuration 15.3.2 Timer1/Timer3 Mode Selection 15.3.3 Software Interrupt Mode 15.3.4 Special Event Trigger FIGURE 15-2: Compare Mode Operation Block Diagram TABLE 15-3: Registers Associated with Capture, Compare, Timer1 and Timer3 15.4 PWM Mode FIGURE 15-3: Simplified PWM Block Diagram FIGURE 15-4: PWM Output 15.4.1 PWM Period EQUATION 15-1: 15.4.2 PWM Duty Cycle EQUATION 15-2: EQUATION 15-3: TABLE 15-4: Example PWM Frequencies and Resolutions at 40 MHz 15.4.3 PWM Auto-Shutdown (CCP1 Only) 15.4.4 Setup for PWM Operation TABLE 15-5: Registers Associated with PWM and Timer2 16.0 Enhanced Capture/Compare/PWM (ECCP) Module Register 16-1: CCP1CON: ECCP Control Register (40/44-Pin Devices) 16.1 ECCP Outputs and Configuration 16.1.1 ECCP Modules and Timer Resources 16.2 Capture and Compare Modes 16.2.1 Special Event Trigger 16.3 Standard PWM Mode TABLE 16-1: Pin Assignments for Various ECCP1 Modes 16.4 Enhanced PWM Mode 16.4.1 PWM Period EQUATION 16-1: FIGURE 16-1: Simplified Block Diagram of the Enhanced PWM Module 16.4.2 PWM Duty Cycle EQUATION 16-2: EQUATION 16-3: 16.4.3 PWM Output Configurations TABLE 16-2: Example PWM Frequencies and Resolutions at 40 MHz FIGURE 16-2: PWM Output Relationships (Active-High State) FIGURE 16-3: PWM Output Relationships (Active-Low State) 16.4.4 Half-Bridge Mode FIGURE 16-4: Half-Bridge PWM Output FIGURE 16-5: Examples of Half-Bridge Output Mode Applications 16.4.5 Full-Bridge Mode FIGURE 16-6: Full-Bridge PWM Output FIGURE 16-7: Example of Full-Bridge Application FIGURE 16-8: PWM Direction Change FIGURE 16-9: PWM Direction Change at Near 100% Duty Cycle 16.4.6 Programmable Dead-Band Delay 16.4.7 Enhanced PWM Auto-Shutdown Register 16-2: ECCP1DEL: PWM Dead-Band Delay Register Register 16-3: ECCP1AS: Enhanced Capture/Compare/PWM Auto-Shutdown Control Register 16.4.8 Start-up Considerations FIGURE 16-10: PWM Auto-Shutdown (PRSEN = 1, Auto-Restart Enabled) FIGURE 16-11: PWM Auto-Shutdown (PRSEN = 0, Auto-Restart Disabled) 16.4.9 Setup for PWM Operation 16.4.10 Operation in Power-Managed Modes 16.4.11 Effects of a Reset TABLE 16-3: Registers Associated with ECCP Module And Timer1 to Timer3 17.0 Universal Serial Bus (USB) 17.1 Overview of the USB Peripheral FIGURE 17-1: USB Peripheral and Options 17.2 USB Status and Control 17.2.1 USB Control Register (UCON) Register 17-1: UCON: USB Control Register 17.2.2 USB Configuration Register (UCFG) FIGURE 17-2: Typical External Transceiver with Isolation Register 17-2: UCFG: USB Configuration Register TABLE 17-1: Differential Outputs to Transceiver TABLE 17-2: Single-Ended Inputs From Transceiver FIGURE 17-3: External Circuitry 17.2.3 USB Status Register (USTAT) FIGURE 17-4: USTAT FIFO Register 17-3: USTAT: USB Status Register 17.2.4 USB Endpoint Control Register 17-4: UEPn: USB Endpoint n Control Register (UEP0 Through UEP15) 17.2.5 USB Address Register (UADDR) 17.2.6 USB Frame Number Registers (UFRMH:UFRML) 17.3 USB RAM FIGURE 17-5: Implementation of USB RAM in Data Memory Space 17.4 Buffer Descriptors and the Buffer Descriptor Table 17.4.1 BD Status and Configuration FIGURE 17-6: Example of a Buffer Descriptor TABLE 17-3: Effect of DTSEN Bit on Odd/Even (DATA0/DATA1) Packet Reception Register 17-5: BDnSTAT: Buffer Descriptor n Status Register (BD0STAT Through BD63STAT), CPU Mode (Data is Written to the Side) 17.4.2 BD Byte Count 17.4.3 BD Address Validation Register 17-6: BDnSTAT: Buffer Descriptor n Status Register (BD0STAT Through BD63STAT), SIE Mode (Data Returned By the Side to the Microcontroller) 17.4.4 Ping-Pong Buffering FIGURE 17-7: Buffer Descriptor Table Mapping for Buffering Modes TABLE 17-4: Assignment of Buffer Descriptors for the Different Buffering Modes TABLE 17-5: Summary of USB Buffer Descriptor Table Registers 17.5 USB Interrupts FIGURE 17-8: USB Interrupt Logic Funnel FIGURE 17-9: Example of a USB Transaction and Interrupt Events 17.5.1 USB Interrupt Status Register (UIR) Register 17-7: UIR: USB Interrupt Status Register EXAMPLE 17-1: Clearing ACTVIF Bit (UIR<2>) 17.5.2 USB Interrupt Enable Register (UIE) Register 17-8: UIE: USB Interrupt Enable Register 17.5.3 USB Error Interrupt Status Register (UEIR) Register 17-9: UEIR: USB Error Interrupt Status Register 17.5.4 USB Error Interrupt Enable Register (UEIE) Register 17-10: UEIE: USB Error Interrupt Enable Register 17.6 USB Power Modes 17.6.1 Bus Power Only FIGURE 17-10: Bus Power Only 17.6.2 Self-Power Only FIGURE 17-11: Self-power Only 17.6.3 Dual Power with Self-Power Dominance FIGURE 17-12: Dual Power Example 17.7 Streaming Parallel Port 17.8 Oscillator 17.9 USB Firmware and Drivers TABLE 17-6: Registers Associated with USB Module Operation(1) 17.10 Overview of USB 17.10.1 Layered Framework 17.10.2 Frames 17.10.3 Transfers 17.10.4 Power FIGURE 17-13: USB Layers 17.10.5 Enumeration 17.10.6 Descriptors 17.10.7 Bus Speed 17.10.8 Class Specifications and Drivers 18.0 Streaming Parallel Port FIGURE 18-1: SPP Data Path 18.1 SPP Configuration 18.1.1 Enabling the SPP Register 18-1: SPPCON: SPP Control Register Register 18-2: SPPCFG: SPP Configuration Register 18.1.2 Clocking Data 18.1.3 Wait States 18.1.4 SPP Pull-ups FIGURE 18-2: Timing for Microcontroller Write Address, Write Data and Read Data (No Wait States) FIGURE 18-3: Timing for USB Write Address and Data (4 Wait States) FIGURE 18-4: Timing for USB Write Address and Read Data (4 Wait States) 18.2 Setup for USB Control 18.3 Setup for Microcontroller Control 18.3.1 SPP Interrupts 18.3.2 Writing to the SPP FIGURE 18-5: Transfer of Data Between USB SIE and SPP 18.3.3 Reading From the SPP Register 18-3: SPPEPS: SPP Endpoint Address and Status Register TABLE 18-1: Registers Associated with the Streaming Parallel Port 19.0 Master Synchronous Serial Port (MSSP) Module 19.1 Master SSP (MSSP) Module Overview 19.2 Control Registers 19.3 SPI Mode FIGURE 19-1: MSSP Block Diagram (SPI Mode) 19.3.1 Registers Register 19-1: SSPSTAT: MSSP Status Register (SPI Mode) Register 19-2: SSPCON1: MSSP Control Register 1 (SPI Mode) 19.3.2 Operation EXAMPLE 19-1: Loading the SSPBUF (SSPSR) Register 19.3.3 Enabling SPI I/O 19.3.4 Typical Connection FIGURE 19-2: SPI Master/Slave Connection 19.3.5 Master Mode EXAMPLE 19-2: LOADING SSPBUF WITH THE TIMER2/2 CLOCK MODE FIGURE 19-3: SPI Mode Waveform (Master Mode) 19.3.6 Slave Mode 19.3.7 Slave Select Synchronization FIGURE 19-4: Slave Synchronization Waveform FIGURE 19-5: SPI Mode Waveform (Slave Mode with CKE = 0) FIGURE 19-6: SPI Mode Waveform (Slave Mode with CKE = 1) 19.3.8 Operation in Power-Managed Modes 19.3.9 Effects of a Reset 19.3.10 Bus Mode Compatibility TABLE 19-1: SPI Bus Modes TABLE 19-2: Registers Associated with SPI Operation 19.4 I2C Mode FIGURE 19-7: MSSP Block Diagram (I2C™ Mode) 19.4.1 Registers Register 19-3: SSPSTAT: MSSP Status Register (I2C™ Mode) Register 19-4: SSPCON1: MSSP Control Register 1 (I2C™ Mode) Register 19-5: SSPCON2: MSSP Control Register 2 (I2C™ Master Mode) Register 19-6: SSPCON2: MSSP Control Register 2 (I2C™ Slave Mode) 19.4.2 Operation 19.4.3 Slave Mode EXAMPLE 19-3: Address Masking Examples FIGURE 19-8: I2C™ Slave Mode Timing with SEN = 0 (Reception, 7-Bit Address) FIGURE 19-9: I2C™ Slave Mode Timing with SEN = 0 and ADMSK<5:1> = 01011 (Reception, 7-bit Address) FIGURE 19-10: I2C™ Slave Mode Timing (Transmission, 7-Bit Address) FIGURE 19-11: I2C™ Slave Mode Timing with SEN = 0 (Reception, 10-Bit Address) FIGURE 19-12: I2C™ Slave Mode Timing with SEN = 0 and ADMSK<5:1> = 01001 (Reception, 10-bit Address) FIGURE 19-13: I2C™ Slave Mode Timing (Transmission, 10-bit Address) 19.4.4 Clock Stretching FIGURE 19-14: Clock Synchronization Timing FIGURE 19-15: I2C™ Slave Mode Timing with SEN = 1 (Reception, 7-Bit Address) FIGURE 19-16: I2C™ Slave Mode Timing with SEN = 1 (Reception, 10-Bit Address) 19.4.5 General Call Address Support FIGURE 19-17: Slave Mode General Call Address Sequence (7 or 10-Bit Addressing Mode) 19.4.6 Master Mode FIGURE 19-18: MSSP Block Diagram (I2C™ Master Mode) 19.4.7 Baud Rate FIGURE 19-19: Baud Rate Generator Block Diagram TABLE 19-3: I2C™ Clock Rate w/BRG FIGURE 19-20: Baud Rate Generator Timing with Clock Arbitration 19.4.8 I2C Master Mode Start Condition Timing FIGURE 19-21: First Start Bit Timing 19.4.9 I2C Master Mode Repeated Start Condition Timing FIGURE 19-22: Repeated Start Condition Waveform 19.4.10 I2C Master Mode Transmission 19.4.11 I2C Master Mode Reception FIGURE 19-23: I2C™ Master Mode Waveform (Transmission, 7 or 10-Bit Address) FIGURE 19-24: I2C™ Master Mode Waveform (Reception, 7-Bit Address) 19.4.12 Acknowledge Sequence Timing 19.4.13 Stop Condition Timing FIGURE 19-25: Acknowledge Sequence Waveform FIGURE 19-26: Stop Condition Receive or Transmit Mode 19.4.14 Sleep Operation 19.4.15 EffectS of a Reset 19.4.16 Multi-Master Mode 19.4.17 Multi -Master Communication, Bus Collision and Bus Arbitration FIGURE 19-27: Bus Collision Timing for Transmit and Acknowledge FIGURE 19-28: Bus Collision During Start Condition (SDA Only) FIGURE 19-29: Bus Collision During Start Condition (SCL = 0) FIGURE 19-30: BRG Reset Due to SDA Arbitration During Start Condition FIGURE 19-31: Bus Collision During a Repeated Start Condition (Case 1) FIGURE 19-32: Bus Collision During Repeated Start Condition (Case 2) FIGURE 19-33: Bus Collision During a Stop Condition (Case 1) FIGURE 19-34: Bus Collision During a Stop Condition (Case 2) TABLE 19-4: Registers Associated with I2C™ Operation 20.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) Register 20-1: TXSTA: Transmit Status And Control Register Register 20-2: RCSTA: Receive Status And Control Register Register 20-3: BAUDCON: Baud Rate Control Register 20.1 Baud Rate Generator (BRG) 20.1.1 Operation in Power-Managed Modes 20.1.2 Sampling TABLE 20-1: Baud Rate Formulas EXAMPLE 20-1: Calculating Baud Rate Error TABLE 20-2: Registers Associated with Baud Rate Generator TABLE 20-3: Baud Rates for Asynchronous Modes 20.1.3 Auto-Baud Rate Detect TABLE 20-4: BRG Counter Clock Rates FIGURE 20-1: Automatic Baud Rate Calculation FIGURE 20-2: BRG Overflow Sequence 20.2 EUSART Asynchronous Mode 20.2.1 EUSART Asynchronous Transmitter FIGURE 20-3: EUSART Transmit Block Diagram FIGURE 20-4: Asynchronous Transmission, TXCKP = 0 (TX Not Inverted) FIGURE 20-5: Asynchronous Transmission (Back to Back), TXCKP = 0 (TX Not Inverted) TABLE 20-5: Registers Associated with Asynchronous Transmission 20.2.2 EUSART Asynchronous Receiver 20.2.3 Setting Up 9-Bit Mode with Address Detect FIGURE 20-6: EUSART Receive Block Diagram FIGURE 20-7: Asynchronous Reception, RXDTP = 0 (RX Not Inverted) TABLE 20-6: Registers Associated with Asynchronous Reception 20.2.4 Auto-Wake-up on Sync Break Character FIGURE 20-8: Auto-Wake-up Bit (WUE) Timings During Normal Operation FIGURE 20-9: Auto-Wake-up Bit (WUE) Timings During Sleep 20.2.5 Break Character Sequence 20.2.6 Receiving A Break Character FIGURE 20-10: Send Break Character Sequence 20.3 EUSART Synchronous Master Mode 20.3.1 EUSART Synchronous Master Transmission FIGURE 20-11: Synchronous Transmission FIGURE 20-12: Synchronous Transmission (Through TXEN) TABLE 20-7: Registers Associated with Synchronous Master Transmission 20.3.2 EUSART Synchronous Master Reception FIGURE 20-13: Synchronous Reception (Master Mode, SREN) TABLE 20-8: Registers Associated with Synchronous Master Reception 20.4 EUSART Synchronous Slave Mode 20.4.1 EUSART Synchronous Slave Transmission TABLE 20-9: Registers Associated with Synchronous Slave Transmission 20.4.2 EUSART Synchronous Slave Reception TABLE 20-10: Registers Associated with Synchronous Slave Reception 21.0 10-Bit Analog-to-Digital Converter (A/D) Module Register 21-1: ADCON0: A/D Control Register 0 Register 21-2: ADCON1: A/D Control Register 1 Register 21-3: ADCON2: A/D Control Register 2 FIGURE 21-1: A/D Block Diagram FIGURE 21-2: A/D Transfer Function FIGURE 21-3: Analog Input Model 21.1 A/D Acquisition Requirements EQUATION 21-1: Acquisition Time EQUATION 21-2: A/D Minimum Charging Time EQUATION 21-3: Calculating the Minimum Required Acquisition Time 21.2 Selecting and Configuring Acquisition Time 21.3 Selecting the A/D Conversion Clock TABLE 21-1: Tad vs. Device Operating Frequencies 21.4 Operation in Power-Managed Modes 21.5 Configuring Analog Port Pins 21.6 A/D Conversions 21.7 Discharge FIGURE 21-4: A/D Conversion Tad Cycles (ACQT<2:0> = 000, Tacq = 0) FIGURE 21-5: A/D Conversion Tad Cycles (ACQT<2:0> = 010, Tacq = 4 Tad) 21.8 Use of the CCP2 Trigger TABLE 21-2: Registers Associated with A/D Operation 22.0 Comparator Module Register 22-1: CMCON: Comparator Control Register 22.1 Comparator Configuration FIGURE 22-1: Comparator I/O Operating Modes 22.2 Comparator Operation 22.3 Comparator Reference FIGURE 22-2: Single Comparator 22.3.1 External Reference Signal 22.3.2 Internal Reference Signal 22.4 Comparator Response Time 22.5 Comparator Outputs FIGURE 22-3: Comparator Output Block Diagram 22.6 Comparator Interrupts 22.7 Comparator Operation During Sleep 22.8 Effects of a Reset 22.9 Analog Input Connection Considerations FIGURE 22-4: Comparator Analog Input Model TABLE 22-1: Registers Associated with Comparator Module 23.0 Comparator Voltage Reference Module 23.1 Configuring the Comparator Voltage Reference Register 23-1: CVRCON: Comparator Voltage Reference Control Register FIGURE 23-1: Comparator Voltage Reference Block Diagram 23.2 Voltage Reference Accuracy/Error 23.3 Operation During Sleep 23.4 Effects of a Reset 23.5 Connection Considerations FIGURE 23-2: Comparator Voltage Reference Output Buffer Example TABLE 23-1: Registers Associated with Comparator Voltage Reference 24.0 High/Low-Voltage Detect (HLVD) Register 24-1: HLVDCON: High/Low-Voltage Detect Control Register 24.1 Operation FIGURE 24-1: HLVD Module Block Diagram (with External Input) 24.2 HLVD Setup 24.3 Current Consumption 24.4 HLVD Start-up Time FIGURE 24-2: Low-Voltage Detect Operation (VDIRMAG = 0) FIGURE 24-3: High-Voltage Detect Operation (VDIRMAG = 1) 24.5 Applications FIGURE 24-4: Typical High/Low-Voltage Detect Application 24.6 Operation During Sleep 24.7 Effects of a Reset TABLE 24-1: Registers Associated with High/Low-Voltage Detect Module 25.0 Special Features of the CPU 25.1 Configuration Bits TABLE 25-1: Configuration Bits and Device IDs Register 25-1: CONFIG1L: CoNfiguration Register 1 Low (Byte Address 300000h) Register 25-2: CONFIG1H: Configuration Register 1 High (Byte Address 300001h) Register 25-3: CONFIG2L: Configuration Register 2 Low (Byte AdDREss 300002h) Register 25-4: CONFIG2H: Configuration Register 2 High (Byte Address 300003h) Register 25-5: CONFIG3H: Configuration Register 3 High (Byte Address 300005h) Register 25-6: CONFIG4L: Configuration Register 4 Low (Byte Address 300006h) Register 25-7: CONFIG5L: Configuration Register 5 Low (Byte Address 300008h) Register 25-8: CONFIG5H: Configuration Register 5 High (Byte Address 300009h) Register 25-9: CONFIG6L: Configuration Register 6 Low (Byte Address 30000Ah) Register 25-10: CONFIG6H: Configuration Register 6 High (Byte Address 30000Bh) Register 25-11: CONFIG7L: Configuration Register 7 Low (Byte Address 30000Ch) Register 25-12: CONFIG7H: Configuration Register 7 High (Byte Address 30000Dh) Register 25-13: DEVID1: Device ID Register 1 for PIC18F2455/2550/4455/4550 Devices Register 25-14: DEVID2: Device ID Register 2 for PIC18F2455/2550/4455/4550 Devices 25.2 Watchdog Timer (WDT) 25.2.1 Control Register FIGURE 25-1: WDT Block Diagram Register 25-15: WDTCON: Watchdog Timer Control Register TABLE 25-2: Summary of Watchdog Timer Registers 25.3 Two-Speed Start-up 25.3.1 Special Considerations for Using Two-Speed Start-up FIGURE 25-2: Timing Transition for Two-Speed Start-up (INTOSC to HSPLL) 25.4 Fail-Safe Clock Monitor FIGURE 25-3: FSCM Block Diagram 25.4.1 FSCM and the Watchdog Timer 25.4.2 Exiting Fail-Safe Operation FIGURE 25-4: FSCM Timing Diagram 25.4.3 FSCM Interrupts in Power-Managed Modes 25.4.4 POR or Wake-up From Sleep 25.5 Program Verification and Code Protection FIGURE 25-5: Code-Protected Program Memory TABLE 25-3: Summary of Code Protection Registers 25.5.1 Program Memory Code Protection FIGURE 25-6: Table Write (WRTx) Disallowed FIGURE 25-7: External Block Table Read (EBTRx) Disallowed FIGURE 25-8: External Block Table Read (EBTRx) Allowed 25.5.2 Data EEPROM Code Protection 25.5.3 Configuration Register Protection 25.6 ID Locations 25.7 In-Circuit Serial Programming 25.8 In-Circuit Debugger TABLE 25-4: Debugger Resources 25.9 Special ICPORT Features (44-Pin TQFP Package Only) 25.9.1 Dedicated ICD/ICSP Port TABLE 25-5: Equivalent Pins for Legacy and Dedicated ICD/ICSP™ Ports 25.9.2 28-Pin Emulation 25.10 Single-Supply ICSP Programming 26.0 Instruction Set Summary 26.1 Standard Instruction Set TABLE 26-1: Opcode Field Descriptions FIGURE 26-1: General Format for Instructions TABLE 26-2: PIC18FXXXX Instruction Set 26.1.1 Standard Instruction Set 26.2 Extended Instruction Set 26.2.1 Extended Instruction Syntax TABLE 26-3: Extensions to the PIC18 Instruction Set 26.2.2 Extended Instruction Set 26.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode 26.2.4 Considerations When Enabling the Extended Instruction Set 26.2.5 Special Considerations with Microchip MPLAB® IDE Tools 27.0 Development Support 27.1 MPLAB Integrated Development Environment Software 27.2 MPASM Assembler 27.3 MPLAB C18 and MPLAB C30 C Compilers 27.4 MPLINK Object Linker/ MPLIB Object Librarian 27.5 MPLAB ASM30 Assembler, Linker and Librarian 27.6 MPLAB SIM Software Simulator 27.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator 27.8 MPLAB REAL ICE In-Circuit Emulator System 27.9 MPLAB ICD 2 In-Circuit Debugger 27.10 MPLAB PM3 Device Programmer 27.11 PICSTART Plus Development Programmer 27.12 PICkit 2 Development Programmer 27.13 Demonstration, Development and Evaluation Boards 28.0 Electrical Characteristics Absolute Maximum Ratings(†) FIGURE 28-1: PIC18F2455/2550/4455/4550 Voltage-Frequency Graph (Industrial) FIGURE 28-2: PIC18LF2455/2550/4455/4550 Voltage-Frequency Graph (Industrial Low Voltage) 28.1 DC Characteristics: Supply Voltage PIC18F2455/2550/4455/4550 (Industrial) PIC18LF2455/2550/4455/4550 (Industrial) 28.2 DC Characteristics: Power-Down and Supply Current PIC18F2455/2550/4455/4550 (Industrial) PIC18LF2455/2550/4455/4550 (Industrial) 28.3 DC Characteristics: PIC18F2455/2550/4455/4550 (Industrial) PIC18LF2455/2550/4455/4550 (Industrial) TABLE 28-1: Memory Programming Requirements TABLE 28-2: Comparator Specifications TABLE 28-3: Voltage Reference Specifications TABLE 28-4: USB Module Specifications TABLE 28-5: USB Internal Voltage Regulator Specifications FIGURE 28-3: High/Low-Voltage Detect Characteristics TABLE 28-6: High/Low-Voltage Detect Characteristics 28.4 AC (Timing) Characteristics 28.4.1 Timing Parameter Symbology 28.4.2 Timing Conditions TABLE 28-7: Temperature and Voltage Specifications – AC FIGURE 28-4: Load Conditions for Device Timing Specifications 28.4.3 Timing Diagrams And Specifications FIGURE 28-5: External Clock Timing (All Modes Except PLL) TABLE 28-8: External Clock Timing Requirements TABLE 28-9: PLL Clock Timing Specifications (Vdd = 3.0V to 5.5V) TABLE 28-10: AC Characteristics: Internal RC Accuracy PIC18F2455/2550/4455/4550 (Industrial) PIC18LF2455/2550/4455/4550 (Industrial) FIGURE 28-6: CLKO and I/O Timing TABLE 28-11: CLKO and I/O Timing Requirements FIGURE 28-7: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing FIGURE 28-8: Brown-out Reset Timing TABLE 28-12: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements FIGURE 28-9: Timer0 and Timer1 External Clock Timings TABLE 28-13: Timer0 and Timer1 External Clock Requirements FIGURE 28-10: Capture/Compare/PWM Timings (All CCP Modules) TABLE 28-14: Capture/Compare/PWM Requirements (All CCP Modules) FIGURE 28-11: Example SPI Master Mode Timing (CKE = 0) TABLE 28-15: Example SPI Mode Requirements (Master Mode, CKE = 0) FIGURE 28-12: Example SPI Master Mode Timing (CKE = 1) TABLE 28-16: Example SPI Mode Requirements (Master Mode, CKE = 1) FIGURE 28-13: Example SPI Slave Mode Timing (CKE = 0) TABLE 28-17: Example SPI Mode Requirements (Slave Mode Timing, CKE = 0) FIGURE 28-14: Example SPI Slave Mode Timing (CKE = 1) TABLE 28-18: Example SPI Slave Mode Requirements (CKE = 1) FIGURE 28-15: I2C™ Bus Start/Stop Bits Timing TABLE 28-19: I2C™ Bus Start/Stop Bits Requirements (Slave Mode) FIGURE 28-16: I2C™ Bus Data Timing TABLE 28-20: I2C™ Bus Data Requirements (Slave Mode) FIGURE 28-17: Master SSP I2C™ Bus Start/Stop Bits Timing Waveforms TABLE 28-21: Master SSP I2C™ Bus Start/Stop Bits Requirements FIGURE 28-18: Master SSP I2C™ Bus Data Timing TABLE 28-22: Master SSP I2C™ Bus Data Requirements FIGURE 28-19: EUSART Synchronous Transmission (Master/Slave) Timing TABLE 28-23: EUSART Synchronous Transmission Requirements FIGURE 28-20: EUSART Synchronous Receive (Master/Slave) Timing TABLE 28-24: EUSART Synchronous Receive Requirements FIGURE 28-21: USB Signal Timing TABLE 28-25: USB Low-Speed Timing Requirements TABLE 28-26: USB Full-Speed Requirements FIGURE 28-22: Streaming Parallel Port Timing (PIC18F4455/4550) TABLE 28-27: Streaming Parallel Port Requirements (PIC18F4455/4550) TABLE 28-28: A/D Converter Characteristics: PIC18F2455/2550/4455/4550 (Industrial) PIC18LF2455/2550/4455/4550 (Industrial) FIGURE 28-23: A/D Conversion Timing TABLE 28-29: A/D Conversion Requirements 29.0 DC and AC Characteristics Graphs and Tables 30.0 Packaging Information 30.1 Package Marking Information Package Marking Information (Continued) 30.2 Package Details Appendix A: Revision History Revision A (May 2004) Revision B (October 2004) Revision C (February 2006) Revision D (January 2007) Revision E (August 2008) Appendix B: Device Differences TABLE B-1: Device Differences Appendix C: Conversion Considerations Appendix D: Migration From Baseline to Enhanced Devices Appendix E: Migration From Mid-Range to Enhanced Devices Appendix F: Migration From High-End to Enhanced Devices INDEX The Microchip Web Site Customer Change Notification Service Customer Support Reader Response PIC18F2455/2550/4455/4550 Product Identification System Worldwide Sales and Service