Datasheet AD8361 (Analog Devices) - 3

link to page 12 link to page 7 link to page 14 link to page 12 link to page 12 link to page 13 link to page 7
Data Sheet AD8361 SPECIFICATIONS
TA = 25°C, VS = 3 V, fRF = 900 MHz, ground reference output mode, unless otherwise noted.
Table 1. Parameter Condition Min Typ Max Unit
SIGNAL INPUT INTERFACE (Input RFIN) Frequency Range1 2.5 GHz Linear Response Upper Limit VS = 3 V 390 mV rms Equivalent dBm, re 50 Ω 4.9 dBm VS = 5 V 660 mV rms Equivalent dBm, re 50 Ω 9.4 dBm Input Impedance2 225||1 Ω||pF RMS CONVERSION (Input RFIN to Output V rms) Conversion Gain 7.5 V/V rms fRF = 100 MHz, VS = 5 V 6.5 8.5 V/V rms Dynamic Range Error Referred to Best Fit Line3 ±0.25 dB Error4 CW Input, −40°C < TA < +85°C 14 dB ±1 dB Error CW Input, −40°C < TA < +85°C 23 dB ±2 dB Error CW Input, −40°C < TA < +85°C 26 dB CW Input, VS = 5 V, −40°C < TA < +85°C 30 dB Intercept-Induced Dynamic Internal Reference Mode 1 dB Range Reduction5, 6 Supply Reference Mode, VS = 3.0 V 1 dB Supply Reference Mode, VS = 5.0 V 1.5 dB Deviation from CW Response 5.5 dB Peak-to-Average Ratio (IS95 Reverse Link) 0.2 dB 12 dB Peak-to-Average Ratio (W-CDMA 4 Channels) 1.0 dB 18 dB Peak-to-Average Ratio (W-CDMA 15 Channels) 1.2 dB OUTPUT INTERCEPT5 Inferred from Best Fit Line3 Ground Reference Mode (GRM) 0 V at SREF, VS at IREF 0 V fRF = 100 MHz, VS = 5 V −50 +150 mV Internal Reference Mode (IRM) 0 V at SREF, IREF Open 350 mV fRF = 100 MHz, VS = 5 V 300 500 mV Supply Reference Mode (SRM) 3 V at IREF, 3 V at SREF 400 mV VS at IREF, VS at SREF VS/7.5 V fRF = 100 MHz, VS = 5 V 590 750 mV POWER-DOWN INTERFACE PWDN HI Threshold 2.7 ≤ VS ≤ 5.5 V, −40°C < TA < +85°C VS − 0.5 V PWDN LO Threshold 2.7 ≤ VS ≤ 5.5 V, −40°C < TA < +85°C 0.1 V Power-Up Response Time 2 pF at FLTR Pin, 224 mV rms at RFIN 5 μs 100 nF at FLTR Pin, 224 mV rms at RFIN 320 μs PWDN Bias Current <1 μA POWER SUPPLIES Operating Range −40°C < TA < +85°C 2.7 5.5 V Quiescent Current 0 mV rms at RFIN, PWDN Input LO7 1.1 mA Power-Down Current GRM or IRM, 0 mV rms at RFIN, PWDN Input HI <1 μA SRM, 0 mV rms at RFIN, PWDN Input HI 10 × VS μA 1 Operation at arbitrarily low frequencies is possible; see Application Information section. 2 Figure 17 and Figure 47 show impedance versus frequency for the MSOP and SOT-23, respectively. 3 Calculated using linear regression. 4 Compensated for output reference temperature drift; see Application Information section. 5 SOT-23-6L operates in ground reference mode only. 6 The available output swing, and hence the dynamic range, is altered by both supply voltage and reference mode; see Figure 39 and Figure 40. 7 Supply current is input level dependent; see Figure 16. Rev. F | Page 3 of 22 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAMS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS CIRCUIT DESCRIPTION Filtering Offset APPLICATION INFORMATION Basic Connections Output Swing Dynamic Range Input Coupling and Matching Input Coupling Using a Series Resistor Selecting the Filter Capacitor Operation at Low Frequencies Power Consumption, Enable and Power-On Volts to dBm Conversion Output Drive Capability and Buffering OUTPUT REFERENCE TEMPERATURE DRIFT COMPENSATION Extended Frequency Characterization EVALUATION BOARD CHARACTERIZATION SETUPS Equipment Analysis OUTLINE DIMENSIONS ORDERING GUIDE