Datasheet ADL5920 (Analog Devices) - 10

ADL5920 Data Sheet Pin No. Mnemonic Description
12 DECL Internal Decoupling Node. Decouple this pin with a 0.1 µF capacitor to ground. Do not use the voltage on this pin, nominally 3.2 V, externally to set any bias levels. In dc-coupled applications where VNEGx is connected to −2.5 V, this pin must be connected directly to ground. 15 VTGT RMS Target Voltage. The voltage applied to this pin sets the target RF level at the output of the internal voltage control ed amplifiers that drive the internal squaring cells of the rms detectors. The recommended voltage for VTGT is 1 V. Increasing VTGT above 1 V degrades the rms accuracy of the ADL5920. Reducing VTGT below 1 V can improve the rms accuracy for signals with high crest factors. The voltage on this pin can be derived from a resistor divider circuit that is driven by the VREF pin (Pin 19). 19 VREF Reference Voltage Output. This voltage reference has a nominal value of 2.5 V. This reference output voltage can set the voltage to the TADJI, TADJS, VTGT, and VOCM pins. 20 TADJI RMS Detector Temperature Compensation. Use this pin to fine tune the temperature intercept stability of the rms detectors. The voltage applied to this pin can be derived from VREF using a simple resistor divider. 25, 26, 31, 32 RFOUT, RFIN RF Inputs and Outputs. The two RFIN pins are common inputs that must always be connected to each other. Likewise, the two RFOUT pins must always be connected to each other. The power of the incident signal on RFIN is measured on the VRMSF pin, and the power on the incident signal into RFOUT is measured on the VRMSR pin. The ratio of the incident signals on RFIN and RFOUT is measured on the VDIFF+ and VDIFF− pins. The RFIN and RFOUT pins are interchangeable, allowing the source signal to drive into RFOUT with the load connected to RFIN. RFIN and RFOUT are normally ac-coupled to the source and load. RFIN and RFOUT can be dc-coupled by connecting a −2.5 V supply to the two VNEGx pins and by connecting the DECL pin to ground. EPAD Exposed Pad. Connect the exposed pad to a ground plane with low thermal and electrical impedance. Rev. B | Page 10 of 26 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Applications Information Basic Connections CHPR± and CHPF± Capacitors VREF Interface VDIFF Output Interface Temperature Drift Compensation Setting VTGT Choosing Values for CRMSF and CRMSR RF Power and Return Loss Calculation DC-Coupled Operation Evaluation Board Outline Dimensions Ordering Guide