Preliminary Datasheet SLG47105 (Dialog Semiconductor) - 8

SLG47105
GreenPAK Programmable Mixed-Signal Matrix with High
Voltage Features Preliminary Tables
Table 1: Pin Description .11
Table 2: Pin Type Definitions .12
Table 3: Absolute Maximum Ratings.13
Table 4: Electrostatic Discharge Ratings .13
Table 5: Recommended Operating Conditions .14
Table 6: Recommended Operating Conditions .14
Table 7: EC at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted.14
Table 8: I2C Pins Timing Characteristics T = -40 °C to +150 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted.18
Table 9: Typical Current Estimated for Each Macrocell at T = 25 °C.19
Table 10: HV Output Electrical Characteristic (H-Bridge or Half-Bridge Modes) .19
Table 11: HV Output Electrical Characteristic (Pre-driver Mode).21
Table 12: Protection Circuits .23
Table 13: Typical Startup Estimated for Chip at T = 25 °C .24
Table 14: Typical Delay Estimated for Each Macrocell at T = 25 °C.24
Table 15: Programmable Delay Expected Typical Delays and Widths at T = 25 °C.26
Table 16: Typical Filter Rejection Pulse Width at T = 25 °C .26
Table 17: LP_BG Specifications at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V.26
Table 18: Typical Counter/Delay Offset at T = 25 °C .26
Table 19: Oscillators Frequency Limits, VDD = 2.3 V to 5.5 V.27
Table 20: Oscillators Power-On Delay at T = 25 °C, OSC Power Setting: "Auto Power-On" .27
Table 21: Current Sense Comparator Specifications at T = -40 °C to +85 °C, VDD = 2.3 to 5.5 V Unless Otherwise Noted.27
Table 22: Differential Amplifier Specifications at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted .29
Table 23: ACMP Specifications at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted.30
Table 24: TS Output vs Temperature (Output Range 1) .32
Table 25: TS Output vs Temperature (Output Range 2) .33
Table 26: GPIO2 Mode Selection.40
Table 27: GPIO3 Mode Selection.40
Table 28: H-Bridge Logic Control Selection Register = 0 (IN-IN Mode).46
Table 29: H-Bridge Logic Control Selection Register = 1 (PH-EN Mode) .46
Table 30: PWM Control of Motor Speed (IN-IN Mode).47
Table 31: PWM Control of Motor Speed (PH-EN Mode).47
Table 32: Half-Bridge Logic.49
Table 33: Matrix Input Table.57
Table 34: Matrix Output Table.59
Table 35: Connection Matrix Virtual Inputs .62
Table 36: 2-bit LUT0 Truth Table .65
Table 37: 2-bit LUT1 Truth Table .65
Table 38: 2-bit LUT2 Truth Table .65
Table 39: 2-bit LUT Standard Digital Functions .65
Table 40: 2-bit LUT1 Truth Table .68
Table 41: 2-bit LUT Standard Digital Functions .68
Table 42: 3-bit LUT0 Truth Table .72
Table 43: 3-bit LUT4 Truth Table .72
Table 44: 3-bit LUT3 Truth Table .72
Table 45: 3-bit LUT5 Truth Table .72
Table 46: 3-bit LUT Standard Digital Functions .72
Table 47: 3-bit LUT1 Truth Table .76
Table 48: 3-bit LUT2 Truth Table .76
Table 49: 3-bit LUT Standard Digital Functions .76
Table 50: 3-bit LUT6 Truth Table .85
Table 51: 4-bit LUT0 Truth Table .87
Table 52: 4-bit LUT Standard Digital Functions .87
Table 53: 3-bit LUT7 Truth Table .94
Table 54: 3-bit LUT9 Truth Table .94
Table 55: 3-bit LUT8 Truth Table .94
Table 56: 3-bit LUT10 Truth Table .94
Table 57: 4-bit LUT1 Truth Table .97
Table 58: 4-bit LUT Standard Digital Functions .97
Table 59: Regular/Preset Mode Registers .120
Table 60: Conditions for Disabling/Enabling an Internal Oscillator .120
Table 61: PWM0 Register Settings .125 Datasheet
CFR0011-120-00 Revision 2.0
8 of 223 9-Jun-2020
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