Datasheet LT4356-3 (Analog Devices) - 10

LT4356-3
APPLICATIONS INFORMATION
The LT4356-3 can limit the voltage and current to the load
Overcurrent Fault
circuitry during supply transients or overcurrent events. The LT4356-3 features an adjustable current limit that The total fault timer period should be set to ride through protects against short circuits or excessive load current. short overvoltage transients while not causing damage During an overcurrent event, the GATE pin is regulated to to the pass transistor. The selection of this N-channel limit the current sense voltage across the V MOSFET pass transistor is critical for this application. CC and SNS pins to 50mV. It must stay on and provide a low impedance path from the input supply to the load during normal operation and An overcurrent fault occurs when the current limit circuitry then dissipate power during overvoltage or overcurrent has been engaged for longer than the time-out delay set conditions. by the timer capacitor. The GATE pin is then immediately pulled low by a 10mA current to GND turning off the The following sections describe the overcurrent and the MOSFET. The GATE pin stays low until the SHDN pin is overvoltage faults, and the selection of the timer capacitor pulled low for at least 100µs and pulled high with a slew value based on the required warning time. The selection rate faster than 10V/ms. of the N-channel MOSFET pass transistor is discussed next. Auxiliary amplifier, reverse input, and the shutdown
Fault Timer
functions are covered after the MOSFET selection. External component selection is discussed in detail in the Design The LT4356-3 includes an adjustable fault timer pin. Con- Example section. necting a capacitor from the TMR pin to ground sets the delay timer period before the MOSFET is turned off. The
Overvoltage Fault
same capacitor also sets the cool down period before the MOSFET is allowed to turn back on after the fault condition The LT4356-3 limits the voltage at the OUT pin during an has disappeared. overvoltage situation. An internal voltage amplifier regu- lates the GATE pin voltage to maintain a 1.25V threshold at Once a fault condition, either overvoltage or overcurrent, the FB pin. During this period of time, the power MOSFET is detected, a current source charges up the TMR pin. The is still on and continues to supply current to the load. This current level varies depending on the voltage drop across allows uninterrupted operation during short overvoltage the drain and source terminals of the power MOSFET(VDS), transient events. which is typically from the VCC pin to the OUT pin. This scheme takes better advantage of the available Safe Oper- When the voltage regulation loop is engaged for longer ating Area (SOA) of the MOSFET than would a fixed timer than the time-out period, set by the timer capacitor con- current. The timer function operates down to VCC = 5V nected from the TMR pin to ground, an overvoltage fault across the whole temperature range. is detected. The GATE pin is pulled down to the OUT pin by a 150mA current. This prevents the power MOSFET from being damaged during a long period of overvoltage, such as during load dump in automobiles. Pulling the SHDN pin low for at least 100µs and pulled high with a slew rate faster than 10V/ms will allow the GATE pin to pull back up. Rev D 10 For more information www.analog.com Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Revision History Typical Application .18702 Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related parts