Datasheet LTC4380 (Analog Devices) - 8
| Hersteller | Analog Devices |
| Beschreibung | Low Quiescent Current Surge Stopper |
| Seiten / Seite | 24 / 8 — PIN FUNCTIONS DRN:. GND:. ON:. OUT:. Exposed Pad:. FLT:. SEL:. GATE:. SNS: |
| Revision | C |
| Dateiformat / Größe | PDF / 1.2 Mb |
| Dokumentensprache | Englisch |
PIN FUNCTIONS DRN:. GND:. ON:. OUT:. Exposed Pad:. FLT:. SEL:. GATE:. SNS:
Modelllinie für dieses Datenblatt
- LTC4380CDD-1#PBF LTC4380CDD-1#TRPBF LTC4380CDD-2#PBF LTC4380CDD-2#TRPBF LTC4380CDD-3#PBF LTC4380CDD-3#TRPBF LTC4380CDD-4#PBF LTC4380CDD-4#TRPBF LTC4380CMS-1#PBF LTC4380CMS-1#TRPBF LTC4380CMS-2#PBF LTC4380CMS-2#TRPBF LTC4380CMS-3#PBF LTC4380CMS-3#TRPBF LTC4380CMS-4#PBF LTC4380CMS-4#TRPBF LTC4380HDD-1#PBF LTC4380HDD-1#TRPBF LTC4380HDD-2#PBF LTC4380HDD-2#TRPBF LTC4380HDD-3#PBF LTC4380HDD-3#TRPBF LTC4380HDD-4#PBF LTC4380HDD-4#TRPBF LTC4380HMS-1#PBF LTC4380HMS-1#TRPBF LTC4380HMS-1#WPBF LTC4380HMS-1#WTRPBF LTC4380HMS-2#PBF LTC4380HMS-2#TRPBF LTC4380HMS-2#WPBF LTC4380HMS-2#WTRPBF LTC4380HMS-3#PBF LTC4380HMS-3#TRPBF LTC4380HMS-3#WPBF LTC4380HMS-3#WTRPBF LTC4380HMS-4#PBF LTC4380HMS-4#TRPBF LTC4380HMS-4#WPBF LTC4380HMS-4#WTRPBF LTC4380IDD-1#PBF LTC4380IDD-1#TRPBF LTC4380IDD-2#PBF LTC4380IDD-2#TRPBF LTC4380IDD-3#PBF LTC4380IDD-3#TRPBF LTC4380IDD-4#PBF LTC4380IDD-4#TRPBF LTC4380IMS-1#PBF LTC4380IMS-1#TRPBF LTC4380IMS-1#WPBF LTC4380IMS-1#WTRPBF LTC4380IMS-2#PBF LTC4380IMS-2#TRPBF LTC4380IMS-2#WPBF LTC4380IMS-2#WTRPBF LTC4380IMS-3#PBF LTC4380IMS-3#TRPBF LTC4380IMS-3#WPBF LTC4380IMS-3#WTRPBF LTC4380IMS-4#PBF LTC4380IMS-4#TRPBF LTC4380IMS-4#WPBF LTC4380IMS-4#WTRPBF
Textversion des Dokuments
LTC4380
PIN FUNCTIONS DRN:
External MOSFET Drain-Source Sense. The DRN
GND:
Device Ground. pin voltage tracks the OUT pin. The resulting DRN pin
ON:
Turn-On Control Input. The LTC4380 can be turned current through external resistor RDRN is proportional to on by pulling this pin above 1.05V or by leaving it open to the external MOSFET VDS. The DRN pin current and ∆VSNS allow an internal 1MΩ resistor to turn the part on. Pulling (SNS – OUT) are multiplied internally to produce a TMR the pin below the threshold puts the part in shutdown pin current approximately proportional to the MOSFET's mode and reduces the supply current to 6µA. Limit the ON power dissipation. This reduces the SOA requirement of to ground leakage current to less than 1µA if no external the MOSFET by timing out faster during more severe faults. pull-up is used. The ON pin can be pulled up to 80V or Choose RDRN to limit the current to 1mA at the peak input below GND by 60V without damage. voltage. Connect to OUT if unused.
OUT:
Output Voltage Sense. This pin senses the output
Exposed Pad:
Exposed Pad. May be left open or connected voltage at the output terminal of the current sense resistor. to device ground (GND). An internal clamp limits the voltage in between the GATE
FLT:
Fault Output. This open drain logic output pin pulls and OUT pins to 17V. Bypass the OUT pin with a minimum low after the voltage at the TMR pin has reached the fault of 22µF as close to the pin as possible. threshold of 1.215V. It indicates that the MOSFET is off
SEL:
Gate Clamp Voltage Select for LTC4380-1 and because either the supply voltage has stayed at an elevated LTC4380-2. Connect the SEL pin to GND to set the internal level for an extended period of time (voltage fault) or the gate clamp voltage to 31.5V. Connect it to V device is in an overcurrent condition (current fault). The CC or OUT for a 50V gate clamp voltage. The SEL pin can be pulled up fault output is capable of sinking up to 3mA. Leave open to 80V or below GND by 60V without damage. Connect or tie to GND if unused. SEL to GND for LTC4380-3 and LTC4380-4.
GATE:
Gate Drive for N-Channel MOSFET. The GATE pin is
SNS:
Current Sense Input. Connect to the input terminal pulled up by an internal 20µA charge pump that is regulated of the current sense resistor. The current limit amplifier to 11.5V above the OUT pin. An amplifier controls the GATE controls the GATE pin to limit the current sense voltage pin to limit the current through the MOSFET. The GATE pin to 50mV. This voltage increases to 62mV in a severe fault is clamped during an overvoltage event, thus indirectly when OUT is below 1.5V. A fixed 7µA is added to the TMR limiting the output voltage. The clamp voltage is set to pin current during an overcurrent condition to shorten the 31.5V with SEL = 0V, or 50V when SEL = VCC for the fixed turn-off time. In a severe short condition when the output voltage versions, LTC4380-1/LTC4380-2. The LTC4380-3 voltage is below 1.5V, the extra current increases to 27µA and LTC4380-4 are adjustable versions without the internal to reduce the power dissipation in the MOSFET. ∆VSNS gate clamp. The voltage at the GATE pin is limited to 13.5V (SNS – OUT) must be limited to less than ±5V. Connect above VCC when not in regulation mode. A minimum of to OUT if unused. 47nF of capacitance and 33Ω series resistor at the pin is necessary to compensate the current limit amplifier. To avoid damaging the external MOSFET during an output short, GATE is also clamped internally to 17V above OUT. Rev. C 8 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Package Description Revision History Typical Application Related Parts
PIN FUNCTIONS DRN:
External MOSFET Drain-Source Sense. The DRN
GND:
Device Ground. pin voltage tracks the OUT pin. The resulting DRN pin
ON:
Turn-On Control Input. The LTC4380 can be turned current through external resistor RDRN is proportional to on by pulling this pin above 1.05V or by leaving it open to the external MOSFET VDS. The DRN pin current and ∆VSNS allow an internal 1MΩ resistor to turn the part on. Pulling (SNS – OUT) are multiplied internally to produce a TMR the pin below the threshold puts the part in shutdown pin current approximately proportional to the MOSFET's mode and reduces the supply current to 6µA. Limit the ON power dissipation. This reduces the SOA requirement of to ground leakage current to less than 1µA if no external the MOSFET by timing out faster during more severe faults. pull-up is used. The ON pin can be pulled up to 80V or Choose RDRN to limit the current to 1mA at the peak input below GND by 60V without damage. voltage. Connect to OUT if unused.
OUT:
Output Voltage Sense. This pin senses the output
Exposed Pad:
Exposed Pad. May be left open or connected voltage at the output terminal of the current sense resistor. to device ground (GND). An internal clamp limits the voltage in between the GATE
FLT:
Fault Output. This open drain logic output pin pulls and OUT pins to 17V. Bypass the OUT pin with a minimum low after the voltage at the TMR pin has reached the fault of 22µF as close to the pin as possible. threshold of 1.215V. It indicates that the MOSFET is off
SEL:
Gate Clamp Voltage Select for LTC4380-1 and because either the supply voltage has stayed at an elevated LTC4380-2. Connect the SEL pin to GND to set the internal level for an extended period of time (voltage fault) or the gate clamp voltage to 31.5V. Connect it to V device is in an overcurrent condition (current fault). The CC or OUT for a 50V gate clamp voltage. The SEL pin can be pulled up fault output is capable of sinking up to 3mA. Leave open to 80V or below GND by 60V without damage. Connect or tie to GND if unused. SEL to GND for LTC4380-3 and LTC4380-4.
GATE:
Gate Drive for N-Channel MOSFET. The GATE pin is
SNS:
Current Sense Input. Connect to the input terminal pulled up by an internal 20µA charge pump that is regulated of the current sense resistor. The current limit amplifier to 11.5V above the OUT pin. An amplifier controls the GATE controls the GATE pin to limit the current sense voltage pin to limit the current through the MOSFET. The GATE pin to 50mV. This voltage increases to 62mV in a severe fault is clamped during an overvoltage event, thus indirectly when OUT is below 1.5V. A fixed 7µA is added to the TMR limiting the output voltage. The clamp voltage is set to pin current during an overcurrent condition to shorten the 31.5V with SEL = 0V, or 50V when SEL = VCC for the fixed turn-off time. In a severe short condition when the output voltage versions, LTC4380-1/LTC4380-2. The LTC4380-3 voltage is below 1.5V, the extra current increases to 27µA and LTC4380-4 are adjustable versions without the internal to reduce the power dissipation in the MOSFET. ∆VSNS gate clamp. The voltage at the GATE pin is limited to 13.5V (SNS – OUT) must be limited to less than ±5V. Connect above VCC when not in regulation mode. A minimum of to OUT if unused. 47nF of capacitance and 33Ω series resistor at the pin is necessary to compensate the current limit amplifier. To avoid damaging the external MOSFET during an output short, GATE is also clamped internally to 17V above OUT. Rev. C 8 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Package Description Revision History Typical Application Related Parts