Datasheet LTM4625 (Analog Devices) - 6
| Hersteller | Analog Devices |
| Beschreibung | 20VIN, 5A Step-Down DC/DC μModule (Power Module) Regulator |
| Seiten / Seite | 26 / 6 — PIN FUNCTIONS. PACKAGE ROW AND COLUMN LABELING MAY VARY. AMONG µModule … |
| Revision | D |
| Dateiformat / Größe | PDF / 1.6 Mb |
| Dokumentensprache | Englisch |
PIN FUNCTIONS. PACKAGE ROW AND COLUMN LABELING MAY VARY. AMONG µModule PRODUCTS. REVIEW EACH PACKAGE. LAYOUT CAREFULLY
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link to page 9 link to page 9 LTM4625
PIN FUNCTIONS PACKAGE ROW AND COLUMN LABELING MAY VARY
Input and Output Returns.
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULLY. SGND (B4):
Signal Ground Connection. Tie to GND with minimum distance. Connect FREQ resistor, COMP com-
COMP (A1):
Current Control Threshold and Error Ampli- ponent, MODE, TRACK/SS component, FB resistor to this fier Compensation Point. The current comparator’s trip pin as needed. threshold is linearly proportional to this voltage, whose normal range is from 0.3V to 1.8V. Tie the COMP pins
VOUT (C1, D1-D2, E1-E2):
Power Output Pins. Apply out- together for parallel operation. The device is internally put load between these pins and GND pins. Recommend compensated. Strictly an output pin. Do not drive this pin. placing output decoupling capacitance directly between these pins and GND pins.
TRACK/SS (A2):
Output Tracking and Soft-Start Input. Allows the user to control the rise time of the output volt-
PGOOD (C2):
Output Power Good with Open-Drain Logic. age. Putting a voltage below 0.6V on this pin bypasses the PGOOD is pulled to ground when the voltage on the FB pin internal reference input to the error amplifier, and servos is not within ±10% of the internal 0.6V reference. the FB pin to match the TRACK/SS voltage. Above 0.6V,
MODE (C4):
Operation Mode Select. Tie this pin to INTV the tracking function stops and the internal reference CC to force continuous synchronous operation at all output resumes control of the error amplifier. There’s an internal loads. Tying it to SGND enables discontinuous mode 2µA pull-up current from INTVCC on this pin, so putting a operation at light loads. Do not leave floating. capacitor here provides a soft-start function.
SV RUN (A3):
Run Control Input of the Switching Mode
IN (C5):
Signal VIN. Filtered input voltage to the on-chip 3.3V regulator. Tie this pin to the V Regulator. Enables chip operation by tying RUN above IN pin in most applica- tions or connect SV 1.2V. Pulling it below 1.1V shuts down the part. Do not IN to an external voltage supply of at least 4V which must also be greater than V leave floating. OUT.
V FREQ (A4):
Frequency is set internally to 1MHz. An ex-
IN (D5, E5):
Power Input Pins. Apply input voltage be- tween these pins and GND pins. Recommend placing ternal resistor can be placed from this pin to SGND to input decoupling capacitance directly between V increase frequency, or from this pin to INTV IN pins CC to reduce and GND pins. frequency. See the Applications Information section for frequency adjustment.
INTVCC (E4):
Internal Regulator Output. The internal power drivers and control circuits are powered from this voltage.
FB (B1):
The Negative Input of the Error Amplifier. Inter- This pin is internally decoupled to GND with a 1µF low ESR nally, this pin is connected to VOUT with a 60.4k precision ceramic capacitor. Do not drive this pin. resistor. Different output voltages can be programmed with an additional resistor between the FB and SGND pins.
CLKIN (A5):
External Synchronization Input to Phase Tying the FB pins together allows for parallel operation. Detector of the Switching Mode Regulator. This pin is See the Applications Information for details. internally terminated to SGND with 20k. The phase-locked loop will force the top power NMOS’s turn-on signal to
PHMODE (B2):
Control Input to Phase Selector of the be synchronized with the rising edge of the CLKIN signal. Switching Mode Regulator Channel. This pin determines the phase relationship between internal oscillator and
CLKOUT (B5):
Output Clock Signal for PolyPhase Operation CLKOUT signal. Tie it to INTV of the Switching Mode Regulator. The phase of CLKOUT CC for 2-phase operation, tie it to SGND for 3-phase operation, and tie it to INTV with respect to CLKIN is determined by the state of the CC/2 for 4-phase operation. PHMODE pin. CLKOUT’s peak-to-peak amplitude is INTVCC to GND. Do not drive this pin.
GND (B3, C3, D3-D4, E3):
Power Ground Pins for Both Rev D 6 For more information www.analog.com Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Decoupling Requirements Operation Applications Information Package Description Revision History Package Photo Design Resources Related Parts
PIN FUNCTIONS PACKAGE ROW AND COLUMN LABELING MAY VARY
Input and Output Returns.
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULLY. SGND (B4):
Signal Ground Connection. Tie to GND with minimum distance. Connect FREQ resistor, COMP com-
COMP (A1):
Current Control Threshold and Error Ampli- ponent, MODE, TRACK/SS component, FB resistor to this fier Compensation Point. The current comparator’s trip pin as needed. threshold is linearly proportional to this voltage, whose normal range is from 0.3V to 1.8V. Tie the COMP pins
VOUT (C1, D1-D2, E1-E2):
Power Output Pins. Apply out- together for parallel operation. The device is internally put load between these pins and GND pins. Recommend compensated. Strictly an output pin. Do not drive this pin. placing output decoupling capacitance directly between these pins and GND pins.
TRACK/SS (A2):
Output Tracking and Soft-Start Input. Allows the user to control the rise time of the output volt-
PGOOD (C2):
Output Power Good with Open-Drain Logic. age. Putting a voltage below 0.6V on this pin bypasses the PGOOD is pulled to ground when the voltage on the FB pin internal reference input to the error amplifier, and servos is not within ±10% of the internal 0.6V reference. the FB pin to match the TRACK/SS voltage. Above 0.6V,
MODE (C4):
Operation Mode Select. Tie this pin to INTV the tracking function stops and the internal reference CC to force continuous synchronous operation at all output resumes control of the error amplifier. There’s an internal loads. Tying it to SGND enables discontinuous mode 2µA pull-up current from INTVCC on this pin, so putting a operation at light loads. Do not leave floating. capacitor here provides a soft-start function.
SV RUN (A3):
Run Control Input of the Switching Mode
IN (C5):
Signal VIN. Filtered input voltage to the on-chip 3.3V regulator. Tie this pin to the V Regulator. Enables chip operation by tying RUN above IN pin in most applica- tions or connect SV 1.2V. Pulling it below 1.1V shuts down the part. Do not IN to an external voltage supply of at least 4V which must also be greater than V leave floating. OUT.
V FREQ (A4):
Frequency is set internally to 1MHz. An ex-
IN (D5, E5):
Power Input Pins. Apply input voltage be- tween these pins and GND pins. Recommend placing ternal resistor can be placed from this pin to SGND to input decoupling capacitance directly between V increase frequency, or from this pin to INTV IN pins CC to reduce and GND pins. frequency. See the Applications Information section for frequency adjustment.
INTVCC (E4):
Internal Regulator Output. The internal power drivers and control circuits are powered from this voltage.
FB (B1):
The Negative Input of the Error Amplifier. Inter- This pin is internally decoupled to GND with a 1µF low ESR nally, this pin is connected to VOUT with a 60.4k precision ceramic capacitor. Do not drive this pin. resistor. Different output voltages can be programmed with an additional resistor between the FB and SGND pins.
CLKIN (A5):
External Synchronization Input to Phase Tying the FB pins together allows for parallel operation. Detector of the Switching Mode Regulator. This pin is See the Applications Information for details. internally terminated to SGND with 20k. The phase-locked loop will force the top power NMOS’s turn-on signal to
PHMODE (B2):
Control Input to Phase Selector of the be synchronized with the rising edge of the CLKIN signal. Switching Mode Regulator Channel. This pin determines the phase relationship between internal oscillator and
CLKOUT (B5):
Output Clock Signal for PolyPhase Operation CLKOUT signal. Tie it to INTV of the Switching Mode Regulator. The phase of CLKOUT CC for 2-phase operation, tie it to SGND for 3-phase operation, and tie it to INTV with respect to CLKIN is determined by the state of the CC/2 for 4-phase operation. PHMODE pin. CLKOUT’s peak-to-peak amplitude is INTVCC to GND. Do not drive this pin.
GND (B3, C3, D3-D4, E3):
Power Ground Pins for Both Rev D 6 For more information www.analog.com Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Decoupling Requirements Operation Applications Information Package Description Revision History Package Photo Design Resources Related Parts