Datasheet LTM4626 (Analog Devices) - 9

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APPLICATIONS INFORMATION
The typical LTM4626 application circuit is shown in shown in Figure 2, thus tying one of the internal 60.4k Figure 23. External component selection is primarily deter- resistors to the output. All of the VFB pins tie together with mined by the input voltage, the output voltage and the one programming resistor as shown in Figure 2. maximum load current. Refer to Table 7 for specific exter- See Figure 25 for an example of parallel operation. nal capacitor requirements for a particular application. COMP VOUT 1.2V/24A
VIN to VOUT Step-Down Ratios
LTM4626 There are restrictions in the maximum V + IN and VOUT step- VOSNS down ratios that can be achieved for a given input voltage VFB due to the minimum off-time and minimum on-time limits TRACK/SS of the regulator. The minimum off-time limit imposes a V – OSNS maximum duty cycle which can be calculated as: COMP V D OUT MAX = 1 – (tOFF(MIN) • fSW) LTM4626 V + OSNS where tOFF(MIN) is the minimum off-time, typically 50ns for LTM4626, and f VFB SW (Hz) is the switching frequency. Conversely the minimum on-time limit imposes a minimum RFB TRACK/SS 60.4k duty cycle of the converter which can be calculated as: 0.1µF V – OSNS D 4626 F02 MIN = tON(MIN) • fSW where t
Figure 2. 2-Phase Parallel Configurations
ON(MIN) is the minimum on-time, typically 25ns for LTM4626. In the rare cases where the minimum duty
Input Decoupling Capacitors
cycle is surpassed, the output voltage will still remain The LTM4626 module should be connected to a low AC in regulation, but the switching frequency will decrease impedance DC source. For the regulator, a 10µF input from its programmed value. Note that additional thermal ceramic capacitor is required for RMS ripple current derating may be applied. See the Thermal Considerations decoupling. Bulk input capacitance is only needed when and Output Current Derating section in this data sheet. the input source impedance is compromised by long
Output Voltage Programming
inductive leads, traces or not enough source capacitance. The bulk capacitor can be an aluminum electrolytic capac- The PWM controller has an internal 0.6V reference volt- itor or polymer capacitor. age. As shown in the Block Diagram, a 60.4k internal feed- back resistor connects the V Without considering the inductor ripple current, the RMS OSNS+ and FB pins together. Adding a resistor, R – current of the input capacitor can be estimated as: FB, from FB pin to VOSNS programs the output voltage: I I OUT(MAX) CIN(RMS) = • D • (1–D) 0.6V η% R FB = • 60.4k VOUT – 0.6V where η% is the estimated efficiency of the power module.
Table 1. RFB Resistor Table vs Various Output Voltages Output Decoupling Capacitors VOUT (V) 0.6 1.0 1.2 1.5 1.8 2.5 3.3 5.0
R With an optimized high frequency, high bandwidth design, FB (kΩ) OPEN 90.9 60.4 40.2 30.1 19.1 13.3 8.25 For parallel operation of multiple channels the same feed- only a single low ESR output ceramic capacitor is required back setting resistor can be used for the parallel design. for the LTM4626 to achieve low output ripple voltage and This is done by connecting the V + very good transient response. In extreme cold or hot tem- OSNS to the output as perature or high output voltage case, additional ceramic Rev B For more information www.analog.com 9 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Electrical Characteristics Pin Configuration Typical Performance Characteristics Pin Functions Block Diagram Decoupling Requirements Operation Applications Information Package Description Revision History Package Photo Design Resources Related Parts