Datasheet LTM4668 (Analog Devices) - 5

link to page 8 link to page 8 LTM4668
TYPICAL PERFORMANCE CHARACTERISTICS Start-Up with No Load Start-Up with 1.5A Load Output Ripple
IIN IIN 200mA/DIV 200mA/DIV VOUT 5mV/DIV RUN RUN AC COUPLED 10V/DIV 10V/DIV VOUT VOUT 1V/DIV 1V/DIV 4668 G08 4668 G09 4668 G10 500µs/DIV 500µs/DIV 500ns/DIV VIN = 12V, VOUT = 1.5V, fS = 2.0MHz VIN = 12V, VOUT = 1.5V, fS = 1MHz VIN = 12V, VOUT = 1.5V, fS = 1MHz INPUT CAPACITOR = 2× 22µF + 1× 10µF INPUT CAPACITOR = 2× 22µF + 1× 10µF INPUT CAPACITOR = 2× 22µF + 1× 10µF + 1× 4.7µF CERAMIC + 1× 4.7µF CERAMIC + 1× 47µF CERAMIC OUTPUT CAPACITOR = 1× 47µF CERAMIC OUTPUT CAPACITOR = 1× 47µF CERAMIC OUTPUT CAPACITOR = 1× 47µF CERAMIC CFF = 150pF
PIN FUNCTIONS VIN (A4, B4, F4, G4):
Power Input Pins connect to the drain pulse-skipping operation, and tie MODE/SYNC to a volt- of the internal top MOSFET for each switching mode regula- age between 1V and INTVCC – 1.2V for forced continuous tor channel and the internal 3.3V regulator for the control mode. Furthermore, connecting this pin to an external circuitry. Apply input voltages between these pins and GND clock will synchronize the switch clock to the external pins. Recommend placing input decoupling capacitance clock and put the part in forced continuous mode. Do directly between each of VIN pins and GND pins. not float this pin.
VOUT1 (A1, B1), VOUT2 (A7, B7), VOUT3 (F7, G7), VOUT4 INTVCC (C4):
Internal 5V Regulator Output. The internal
(F1, G1):
Power Output Pins of each switching mode regu- power drivers and control circuits are powered from this lator channel. Apply output load between these pins and voltage. This pin is internally decoupled to GND with a GND pins. Recommend placing output decoupling capaci- 2.2µF low ESR ceramic capacitor. No additional external tance directly between these pins and GND pins. See the decoupling capacitor is needed. INTVCC only starts up if Applications Information section for paralleling outputs. at least one of the RUN pins is high.
GND (A2–A3, A5–A6, B2–B3, B5–B6, C2, C6, D3–D5, RUN1 (C3), RUN2 (C5), RUN3 (E5), RUN4 (E3):
Run
E2, E6, F2–F3, F5–F6, G2–G3, G5–G6):
Power Ground Control Input of each switching mode regulator channel. Pins for both Input and Output Returns. Use large PCB Enable regulator operation by tying the specific RUN pin copper areas to connect all GND together. above 1V. Tying it below 0.35V shuts down the specific regulator channel.
PGOOD1 (D2), PGOOD2 (D6), PGOOD3 (D7), PGOOD4 (D1):
Output Power Good with Open-Drain Logic of each
FB1 (C1), FB2 (C7), FB3 (E7), FB4 (E1):
The Negative switching mode regulator channel. PGOOD is pulled to Input of the Error Amplifier for each switching mode regu- ground when the voltage on the FB pin is not within ±7.5% lator channel. Internally, this pin is connected to VOUT of of the internal 0.6V reference. each channel with a 60.4kΩ precision resistor. Different output voltages can be programmed with an additional
MODE/SYNC (E4):
Burst Mode Select and External Clock resistor between FB and GND pins. In PolyPhase® opera- Synchronization of the switching mode regulator. Tie tion, connect FB pins for all slaves to INTV MODE/SYNC to INTV CC and con- CC for Burst Mode operation with a nect V 400mA peak current clamp. Tie MODE/SYNC to GND for OUT for all paralleled phases together. See the Applications Information section for details. Rev. A For more information www.analog.com 5 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Electrical Characteristics Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Decoupling Requirements Operation Applications Information Package Description Revision History Package Photo Design Resources Related Parts