Datasheet ADuCM3027, ADuCM3029 (Analog Devices) - 3

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Data Sheet ADuCM3027/ ADuCM3029 GENERAL DESCRIPTION
The ADuCM3027/ADuCM3029 microcontroller units (MCUs) To support low dynamic and hibernate power management, the are ultra low power microcontroller systems with integrated ADuCM3027/ADuCM3029 MCUs provide a collection of power management for processing, control, and connectivity. power modes and features, such as dynamic and software The MCU system is based on the ARM® Cortex®-M3 processor, controlled clock gating and power gating. a collection of digital peripherals, embedded SRAM and flash The ADuCM3029-1 and ADuCM3029-2 MCU models share the memory, and an analog subsystem which provides clocking, same features and functionality as that of the ADuCM3029 MCU. reset, and power management capability in addition to an All specifications pertaining to the ADuCM3027 and analog-to-digital converter (ADC) subsystem. For a feature ADuCM3029 are also applicable to the ADuCM3029-1 and comparison across the ADuCM3027/ADuCM3029 product ADuCM3029-2. offerings, see Table 1. For full details on the ADuCM3027/ADuCM3029 MCUs, refer to
Table 1. Product Flash Memory Options
the ADuCM302x Ultra Low Power ARM Cortex-M3 MCU with
Device Embedded Flash Memory Size
Integrated Power Management Hardware Reference Manual. ADuCM3029 256 kB
PRODUCT HIGHLIGHTS
ADuCM3027 128 kB 1. Industry leading ultralow power consumption. System features that are common across the ADuCM3027/ 2. Robust operation, including full voltage monitoring in ADuCM3029/ADuCM3029-1/ADuCM3029-2 MCUs include deep sleep modes, ECC support on flash, and parity error the following: detection on SRAM memory. • Up to 26 MHz ARM Cortex-M3 processor 3. Leading edge security. Fast encryption provides read • Up to 256 kB of embedded flash memory with error protection to customer algorithms. Write protection correction code (ECC) prevents device reprogramming by unauthorized code. • Optional 4 kB cache for lower active power 4. Failure detection of 32 kHz LFXTAL via interrupt. • 64 kB system SRAM with parity 5. SensorStrobe™ for precise time synchronized sampling of • Power management unit (PMU) external sensors. Works in hibernate mode, resulting in • drastic current reduction in system solutions. Current Multilayer advanced microcontroller bus architecture consumption reduces by 10 times when using, for example, (AMBA) bus matrix the ADXL363 accelerometer. Software intervention is not • Central direct memory access (DMA) controller required after setup. No pulse drift due to software execution. • Beeper interface • Serial port (SPORT), serial peripheral interface (SPI), inter-integrated circuit (I2C), and universal asynchronous receiver/transmitter (UART) peripheral interfaces • Cryptographic hardware support with advanced encryption standard (AES) and secure hash algorithm (SHA)-256 • Real-time clock (RTC) • General-purpose and watchdog timers • Programmable general-purpose input/output (GPIO) pins • Hardware cyclic redundancy check (CRC) calculator with programmable generator polynomial • Power-on reset (POR) and power supply monitor (PSM) • 12-bit successive approximation register (SAR) ADC • True random number generator (TRNG) Rev. B | Page 3 of 39 Document Outline Features Applications Functional Block Diagram Revision History General Description Product Highlights Specifications Operating Conditions and Electrical Characteristics Embedded Flash Specifications Power Supply Current Specifications Active Mode Flexi Mode Deep Sleep Modes—VBAT = 3.0 V ADC Specifications System Clocks External Crystal Oscillator Specifications On-Chip RC Oscillator Specifications System Clocks and PLL Specifications Timing Specifications Reset Timing Serial Ports Timing SPI Timing I2C Specifications General-Purpose Port Timing RTC1 (FLEX_RTC) Specifications Timer Pulse-Width Modulation (PWM) Output Cycle Timing Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation ARM Cortex-M3 Processor ARM Cortex-M3 Memory Subsystem Code Region SRAM Region System Region Memory Architecture SRAM Region MMRs (Peripheral Control and Status) Flash Memory Cache Controller System and Integration Features Reset Booting Power Management Power Modes Active Mode Flexi Mode Hibernate Mode Shutdown Mode Security Features Cryptographic Accelerator True Random Number Generator (TRNG) Reliability and Robustness Features ECC Enabled Flash Memory Multiparity Bit Protected SRAM Software Watchdog Cyclic Redundancy Check (CRC) Accelerator Programmable GPIOs Timers General-Purpose Timers Watchdog Timer (WDT) Analog-to-Digital Converter (ADC) Subsystem Clocking Beeper Driver Debug Capability On-Chip Peripheral Features Serial Ports (SPORT) SPI Ports UART Port I2C Development Support Documentation Hardware Software Additional Information Reference Designs MCU Test Conditions Driver Types EEMBC ULPMark™-CP Score GPIO Multiplexing Applications Information About ADuCM3027/ADuCM3029 Silicon Anomalies Functionality Issues Outline Dimensions Ordering Guide