ADuM5401W/ADuM5402W/ADuM5403WData SheetSPECIFICATIONS ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/5 V SECONDARY ISOLATED SUPPLY Typical specifications are at TA = 25°C, VDD1 = VSEL = VISO = 5 V. Minimum/maximum specifications apply over the entire recommended operation range, which is 4.5 V ≤ VDD1, VSEL, VISO ≤ 5.5 V, and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Table 2. DC-to-DC Converter Static Specifications ParameterSymbolMinTypMaxUnitTest Conditions/Comments DC-TO-DC CONVERTER SUPPLY Setpoint VISO 4.7 5.0 5.4 V IISO = 0 mA Line Regulation VISO (LINE) 1 mV/V IISO = 50 mA, VDD1 = 4.5 V to 5.5 V Load Regulation VISO (LOAD) 1 5 % IISO = 10 mA to 90 mA Output Ripple VISO (RIP) 75 mV p-p 20 MHz bandwidth, CBO = 0.1 µF||10 µF, IISO = 90 mA Output Noise VISO (NOISE) 200 mV p-p CBO = 0.1 µF||10 µF, IISO = 90 mA Switching Frequency fOSC 180 MHz PWM Frequency fPWM 625 kHz Output Supply Current IISO (MAX) 100 mA VISO > 4.5 V Efficiency at IISO (MAX) 34 % IISO = 100 mA IDD1, No VISO Load IDD1 (Q) 20 35 mA IDD1, Full VISO Load IDD1 (MAX) 290 mA Table 3. DC-to-DC Converter Dynamic Specifications25 Mbps—C GradeParameterSymbolMinTypMaxUnitTest Conditions/Comments SUPPLY CURRENT Input IDD1 ADuM5401W 68 mA No VISO load ADuM5402W 71 mA No VISO load ADuM5403W 75 mA No VISO load Available to Load IISO (LOAD) ADuM5401W 87 mA ADuM5402W 85 mA ADuM5403W 83 mA Table 4. Switching Specifications ParameterSymbolMinTypMaxUnitTest Conditions/Comments SWITCHING SPECIFICATIONS Data Rate 25 Mbps Within PWD limit Propagation Delay tPHL, tPLH 45 60 ns 50% input to 50% output Pulse Width Distortion PWD 6 ns |tPLH − tPHL| Change vs. Temperature 5 ps/°C Pulse Width PW 40 ns Within PWD limit Propagation Delay Skew tPSK 15 ns Between any two units Channel Matching Codirectional1 tPSKCD 6 ns Opposing Directional2 tPSKOD 15 ns 1 Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. 2 Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. Rev. F | Page 4 of 25 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAMS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/5 V SECONDARY ISOLATED SUPPLY ELECTRICAL CHARACTERISTICS—3.3 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY PACKAGE CHARACTERISTICS REGULATORY APPROVALS INSULATION AND SAFETY-RELATED SPECIFICATIONS DIN EN 69747-5-2 (VDE 0884 TEIL 2) INSULATION CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TRUTH TABLE TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY APPLICATIONS INFORMATION THEORY OF OPERATION PCB LAYOUT THERMAL ANALYSIS PROPAGATION DELAY RELATED PARAMETERS START-UP BEHAVIOR EMI CONSIDERATIONS DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY POWER CONSUMPTION POWER CONSIDERATIONS INSULATION LIFETIME VISO START-UP ISSUES Symptom Cause Solution OUTLINE DIMENSIONS ORDERING GUIDE AUTOMOTIVE PRODUCTS