Datasheet ADuM5401, ADuM5402, ADuM5403, ADuM5404 (Analog Devices) - 4

ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet SPECIFICATIONS ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/5 V SECONDARY ISOLATED SUPPLY
Typical specifications are at TA = 25°C, VDD1 = VSEL = VISO = 5 V. Minimum/maximum specifications apply over the entire recommended operation range which is 4.5 V ≤ VDD1, VSEL, VISO ≤ 5.5 V; and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 2. DC-to-DC Converter Static Specifications Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC-TO-DC CONVERTER SUPPLY Setpoint VISO 4.7 5.0 5.4 V IISO = 0 mA Line Regulation VISO (LINE) 1 mV/V IISO = 50 mA, VDD1 = 4.5 V to 5.5 V Load Regulation VISO (LOAD) 1 5 % IISO = 10 mA to 90 mA Output Ripple VISO (RIP) 75 mV p-p 20 MHz bandwidth, CBO = 0.1 μF||10 μF, IISO = 90 mA Output Noise VISO (NOISE) 200 mV p-p CBO = 0.1 μF||10 μF, IISO = 90 mA Switching Frequency fOSC 180 MHz PWM Frequency fPWM 625 kHz Output Supply Current IISO (MAX) 100 mA VISO > 4.5 V Efficiency at IISO (MAX) 34 % IISO = 100 mA IDD1, No VISO Load IDD1 (Q) 19 30 mA IDD1, Full VISO Load IDD1 (MAX) 290 mA
Table 3. DC-to-DC Converter Dynamic Specifications 1 Mbps—A Grade, C Grade 25 Mbps—C Grade Parameter Symbol Min Typ Max Min Typ Unit Test Max Conditions/Comments
SUPPLY CURRENT Input IDD1 ADuM5401 19 68 mA No VISO load ADuM5402 19 71 mA No VISO load ADuM5403 19 75 mA No VISO load ADuM5404 19 78 mA No VISO load Available to Load IISO (LOAD) ADuM5401 100 87 mA ADuM5402 100 85 mA ADuM5403 100 83 mA ADuM5404 100 81 mA
Table 4. Switching Specifications A Grade C Grade Parameter Symbol Min Typ Max Min Typ Unit Test Max Conditions/Comments
SWITCHING SPECIFICATIONS Data Rate 1 25 Mbps Within PWD limit Propagation Delay tPHL, tPLH 55 100 45 60 ns 50% input to 50% output Pulse Width Distortion PWD 40 6 ns |tPLH − tPHL| Change vs. Temperature 5 ps/°C Pulse Width PW 1000 40 ns Within PWD limit Propagation Delay Skew tPSK 50 15 ns Between any two units Channel Matching Codirectional1 tPSKCD 50 6 ns Opposing Directional2 tPSKOD 50 15 ns 1 Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation 7 barrier. 2 Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. Rev. E | Page 4 of 29 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAMS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/5 V SECONDARY ISOLATED SUPPLY ELECTRICAL CHARACTERISTICS—3.3 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY PACKAGE CHARACTERISTICS REGULATORY INFORMATION INSULATION AND SAFETY-RELATED SPECIFICATIONS IEC 60747-5-2 (VDE 0884, PART 2):2003-01 INSULATION CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TRUTH TABLE TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY APPLICATIONS INFORMATION PCB LAYOUT THERMAL ANALYSIS PROPAGATION DELAY-RELATED PARAMETERS START-UP BEHAVIOR EMI CONSIDERATIONS DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY POWER CONSUMPTION POWER CONSIDERATIONS INCREASING AVAILABLE POWER INSULATION LIFETIME OUTLINE DIMENSIONS ORDERING GUIDE NOTES NOTES