Datasheet AD7294 (Analog Devices) - 8

AD7294 Data Sheet GENERAL SPECIFICATIONS
AVDD = DVDD = 4.5 V to 5.5 V, AGND = DGND = 0 V, VREF = 2.5 V internal or external; VDRIVE = 2.7 V to 5.5 V; VPP = AVDD to 59.4 V; DAC OUTV+ AB and DAC OUTV+ CD = 4.5 V to 16.5 V; OFFSET IN x is floating, therefore, DAC output span = 0 V to 5 V; TA = −40°C to +105°C, unless otherwise noted.
Table 3. Parameter Min Typ Max Unit Test Conditions/Comments
LOGIC INPUTS Input High Voltage, VIH 0.7 VDRIVE V SDA, SCL only Input Low Voltage, VIL 0.3 VDRIVE V SDA, SCL only Input Leakage Current, IIN ±1 µA Input Hysteresis, VHYST 0.05 VDRIVE V Input Capacitance, CIN 8 pF Glitch Rejection 50 ns Input filtering suppresses noise spikes of less than 50 ns I2C Address Pins Maximum External 30 pF Tristate input Capacitance if Floating LOGIC OUTPUTS SDA, ALERT SDA and ALERT/BUSY are open-drain outputs Output Low Voltage, VOL 0.4 V ISINK = 3 mA 0.6 V ISINK = 6 mA Floating-State Leakage Current ±1 µA Floating-State Output Capacitance 8 pF ISENSE OVERRANGE ISENSE OVERRANGE is a push-pull output Output High Voltage, VOH VDRIVE − 0.2 V ISOURCE = 200 µA for push-pull outputs Output Low Voltage, VOL 0.2 V ISINK = 200 µA for push-pull outputs Overrange Setpoint VFS VFS × 1.2 mV VFS = ±VREF ADC/12.5 POWER REQUIREMENTS VPP AVDD 59.4 V AVDD 4.5 5.5 V V(+) 4.5 16.5 V DVDD 4.5 5.5 V Tie DVDD to AVDD VDRIVE 2.7 5.5 V IDD Dynamic 5.3 6.5 mA AVDD + DVDD + VDRIVE, DAC outputs unloaded DAC OUTV+ x, IDD 0.6 1.2 mA At midscale output voltage, DAC outputs unloaded Power Dissipation 70 105 mW Power-Down IDD 0.5 1 µA For each AVDD and VDRIVE DIDD 1 16.5 µA DAC OUTV+ x, IDD 35 60 µA Power Dissipation 2.5 mW Rev. I | Page 8 of 47 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS DAC SPECIFICATIONS ADC SPECIFICATIONS GENERAL SPECIFICATIONS TIMING CHARACTERISTICS I2C Serial Interface Timing and Circuit Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY DAC TERMINOLOGY ADC TERMINOLOGY THEORY OF OPERATION ADC OVERVIEW ADC TRANSFER FUNCTIONS ANALOG INPUTS Single-Ended Mode Differential Mode Driving Differential Inputs Using an Op Amp Pair Pseudo Differential Mode CURRENT SENSOR Choosing RSENSE Current Sense Filtering Kelvin Sense Resistor Connection ANALOG COMPARATOR LOOP TEMPERATURE SENSOR Remote Sensing Diode Ideality Factor Base Emitter Voltage Base Resistance hFE Variation Series Resistance Cancellation DAC OPERATION Resistor String Output Amplifier ADC AND DAC REFERENCE VDRIVE FEATURE REGISTER SETTING ADDRESS POINTER REGISTER COMMAND REGISTER (0x00) RESULT REGISTER (0x01) ADC Channel Allocation TSENSE1, TSENSE2 RESULT REGISTERS (0X02 AND 0X03) TSENSEINT RESULT REGISTER (0X04) Temperature Value Format DACA, DACB, DACC, DACD, REGISTERS (0x01 TO 0x04) ALERT STATUS REGISTER A (0x05), REGISTER B (0x06), AND REGISTER C (0x07) CHANNEL SEQUENCE REGISTER (0x08) CONFIGURATION REGISTER (0x09) Sample Delay and Bit Trial Delay POWER-DOWN REGISTER (0x0A) DATAHIGH/DATALOW REGISTERS: 0x0B, 0x0C (VIN0); 0x0E, 0x0F (VIN1); 0x11, 0x12 (VIN2); 0x14, 0x15 (VIN3) HYSTERESIS REGISTERS: 0X0D (VIN0), 0X10 (VIN1), 0X13 (VIN2), 0X16 (VIN3) TSENSE OFFSET REGISTERS (0x26 AND 0x27) I2C INTERFACE GENERAL I2C TIMING SERIAL BUS ADDRESS BYTE INTERFACE PROTOCOL Writing a Single Byte of Data to an 8-Bit Register Writing Two Bytes of Data to a 16-Bit Register Writing to Multiple Registers Reading Data from an 8-Bit Register Reading Two Bytes of Data from a 16-Bit Register MODES OF OPERATION COMMAND MODE AUTOCYCLE MODE ALERTS AND LIMITS THEORY ALERT_FLAG BIT ALERT STATUS REGISTERS DATAHIGH AND DATALOW MONITORING FEATURES HYSTERESIS Using the Limit Registers to Store Minimum/Maximum Conversion Results APPLICATIONS INFORMATION BASE STATION POWER AMPLIFIER MONITOR AND CONTROL GAIN CONTROL OF POWER AMPLIFIER LAYOUT AND CONFIGURATION POWER SUPPLY BYPASSING AND GROUNDING Layout Considerations for External Temperature Sensors OUTLINE DIMENSIONS ORDERING GUIDE