Datasheet AD7292 (Analog Devices) - 2
| Hersteller | Analog Devices |
| Beschreibung | 10-Bit Monitor & Control System with ADC, DACs, Temperature Sensor and GPIOs |
| Seiten / Seite | 40 / 2 — AD7292. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY 9/14—Rev. 0 to … |
| Revision | A |
| Dateiformat / Größe | PDF / 695 Kb |
| Dokumentensprache | Englisch |
AD7292. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY 9/14—Rev. 0 to Rev. A. 10/12—Revision 0: Initial Version
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AD7292 Data Sheet TABLE OF CONTENTS
Features .. 1 ADC Sequence Register (Address 0x03) ... 21 Applications ... 1 Configuration Register Bank (Address 0x05) .. 21 Functional Block Diagram .. 1 Alert Limits Register Bank (Address 0x06) .. 30 General Description ... 1 Alert Flags Register Bank (Address 0x07) .. 31 Revision History ... 2 Minimum and Maximum Register Bank (Address 0x08) .. 32 Specifications ... 3 Offset Register Bank (Address 0x09) ... 32 ADC Specifications .. 3 DAC Buffer Enable Register (Address 0x0A) ... 33 DAC Specifications... 4 GPIO Register (Address 0x0B) ... 33 General Specifications ... 5 Conversion Command Register (Address 0x0E) ... 34 Temperature Sensor Specifications .. 5 ADC Conversion Result Registers, VIN0 to VIN7 Timing Specifications .. 6 (Address 0x10 to Address 0x17) ... 34 Absolute Maximum Ratings .. 7 TSENSE Conversion Result Register (Address 0x20) .. 34 Thermal Resistance .. 7 DAC Channel Registers (Address 0x30 to Address 0x33) .. 34 ESD Caution .. 7 ADC Conversion Control ... 35 Pin Configuration and Function Descriptions ... 8 ADC Conversion Command .. 35 Typical Performance Characteristics ... 10 ADC Sequencer .. 36 Theory of Operation .. 15 DAC Output Control ... 37 Analog Inputs .. 15 LDAC Operation .. 37 ADC Transfer Functions ... 16 Simultaneous Update of All DAC Outputs ... 37 Temperature Sensor ... 17 Alerts and Limits .. 38 DAC Operation ... 17 Alert Limit Monitoring Features .. 38 Digital I/O Pins ... 17 Hardware Alert Pins... 38 Serial Port Interface (SPI) .. 18 Alert Flag Bits in the Conversion Result Registers .. 38 Interface Protocol ... 18 Alert Flags Register Bank .. 39 Register Structure ... 20 Minimum and Maximum Conversion Results .. 39 Register Descriptions ... 21 Outline Dimensions ... 40 Vendor ID Register (Address 0x00) ... 21 Ordering Guide .. 40 ADC Data Register (Address 0x01) ... 21
REVISION HISTORY 9/14—Rev. 0 to Rev. A
Changes to VIN ALERT0 Routing and VIN ALERT1 Routing Changes to Figure 2 .. 6 Subregisters (Address 0x15 and Address 0x16) Section, Changed t Table 25, and Table 26 .. 27 11 from 4 ns max to 4 ns min and Removed Endnote 4; Table 5 .. 21 Changes to Figure 40 and Figure 41 .. 35 Changes to Figure 35 .. 18 Changes to Figure 42 .. 36 Changes to Table 15 .. 21
10/12—Revision 0: Initial Version
Changes to VIN Filter Subregister (Address 0x13) Section, Conversion Delay Control Subregister (Address 0x14) Section, Table 23, and Table 24 .. 26 Rev. A | Page 2 of 40 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications ADC Specifications DAC Specifications General Specifications Temperature Sensor Specifications Timing Specifications Timing Diagram Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Analog Inputs Single-Ended Mode Differential Mode ADC Transfer Functions Temperature Sensor DAC Operation Digital I/O Pins GPIO0/ALERT0 and GPIO1/ALERT1 Pins GPIO2/DAC DISABLE0 and GPIO4/DAC DISABLE1 Pins GPIO3/LDAC Pin GPIO6/BUSY Pin Serial Port Interface (SPI) Interface Protocol Register Structure Register Descriptions Vendor ID Register (Address 0x00) ADC Data Register (Address 0x01) ADC Sequence Register (Address 0x03) Configuration Register Bank (Address 0x05) Digital Output Driver Subregister (Address 0x01) Digital I/O Function Subregister (Address 0x02) General Subregister (Address 0x08) VIN RANGE0 and VIN RANGE1 Subregisters (Address 0x10 and Address 0x11) ADC Sampling Mode Subregister (Address 0x12) VIN Filter Subregister (Address 0x13) Conversion Delay Control Subregister (Address 0x14) VIN ALERT0 Routing and VIN ALERT1 Routing Subregisters (Address 0x15 and Address 0x16) Temperature Sensor Subregister (Address 0x20) Temperature Sensor Alert Routing Subregister (Address 0x21) GPIO2/DAC DISABLE0 and GPIO4/DAC DISABLE1 Subregisters (Address 0x30 and Address 0x31) Alert Limits Register Bank (Address 0x06) Alert High Limit and Alert Low Limit Subregisters Hysteresis Subregisters Alert Flags Register Bank (Address 0x07) ADC Alert Flags and TSENSE Alert Flags Subregisters (Address 0x00 and Address 0x02) Minimum and Maximum Register Bank (Address 0x08) Offset Register Bank (Address 0x09) DAC Buffer Enable Register (Address 0x0A) GPIO Register (Address 0x0B) Conversion Command Register (Address 0x0E) ADC Conversion Result Registers, VIN0 to VIN7 (Address 0x10 to Address 0x17) TSENSE Conversion Result Register (Address 0x20) DAC Channel Registers (Address 0x30 to Address 0x33) ADC Conversion Control ADC Conversion Command ADC Sequencer DAC Output Control LDAC Operation Simultaneous Update of All DAC Outputs Alerts and Limits Alert Limit Monitoring Features Hysteresis Hardware Alert Pins Alert Flag Bits in the Conversion Result Registers Alert Flags Register Bank Minimum and Maximum Conversion Results Outline Dimensions Ordering Guide
AD7292 Data Sheet TABLE OF CONTENTS
Features .. 1 ADC Sequence Register (Address 0x03) ... 21 Applications ... 1 Configuration Register Bank (Address 0x05) .. 21 Functional Block Diagram .. 1 Alert Limits Register Bank (Address 0x06) .. 30 General Description ... 1 Alert Flags Register Bank (Address 0x07) .. 31 Revision History ... 2 Minimum and Maximum Register Bank (Address 0x08) .. 32 Specifications ... 3 Offset Register Bank (Address 0x09) ... 32 ADC Specifications .. 3 DAC Buffer Enable Register (Address 0x0A) ... 33 DAC Specifications... 4 GPIO Register (Address 0x0B) ... 33 General Specifications ... 5 Conversion Command Register (Address 0x0E) ... 34 Temperature Sensor Specifications .. 5 ADC Conversion Result Registers, VIN0 to VIN7 Timing Specifications .. 6 (Address 0x10 to Address 0x17) ... 34 Absolute Maximum Ratings .. 7 TSENSE Conversion Result Register (Address 0x20) .. 34 Thermal Resistance .. 7 DAC Channel Registers (Address 0x30 to Address 0x33) .. 34 ESD Caution .. 7 ADC Conversion Control ... 35 Pin Configuration and Function Descriptions ... 8 ADC Conversion Command .. 35 Typical Performance Characteristics ... 10 ADC Sequencer .. 36 Theory of Operation .. 15 DAC Output Control ... 37 Analog Inputs .. 15 LDAC Operation .. 37 ADC Transfer Functions ... 16 Simultaneous Update of All DAC Outputs ... 37 Temperature Sensor ... 17 Alerts and Limits .. 38 DAC Operation ... 17 Alert Limit Monitoring Features .. 38 Digital I/O Pins ... 17 Hardware Alert Pins... 38 Serial Port Interface (SPI) .. 18 Alert Flag Bits in the Conversion Result Registers .. 38 Interface Protocol ... 18 Alert Flags Register Bank .. 39 Register Structure ... 20 Minimum and Maximum Conversion Results .. 39 Register Descriptions ... 21 Outline Dimensions ... 40 Vendor ID Register (Address 0x00) ... 21 Ordering Guide .. 40 ADC Data Register (Address 0x01) ... 21
REVISION HISTORY 9/14—Rev. 0 to Rev. A
Changes to VIN ALERT0 Routing and VIN ALERT1 Routing Changes to Figure 2 .. 6 Subregisters (Address 0x15 and Address 0x16) Section, Changed t Table 25, and Table 26 .. 27 11 from 4 ns max to 4 ns min and Removed Endnote 4; Table 5 .. 21 Changes to Figure 40 and Figure 41 .. 35 Changes to Figure 35 .. 18 Changes to Figure 42 .. 36 Changes to Table 15 .. 21
10/12—Revision 0: Initial Version
Changes to VIN Filter Subregister (Address 0x13) Section, Conversion Delay Control Subregister (Address 0x14) Section, Table 23, and Table 24 .. 26 Rev. A | Page 2 of 40 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications ADC Specifications DAC Specifications General Specifications Temperature Sensor Specifications Timing Specifications Timing Diagram Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Analog Inputs Single-Ended Mode Differential Mode ADC Transfer Functions Temperature Sensor DAC Operation Digital I/O Pins GPIO0/ALERT0 and GPIO1/ALERT1 Pins GPIO2/DAC DISABLE0 and GPIO4/DAC DISABLE1 Pins GPIO3/LDAC Pin GPIO6/BUSY Pin Serial Port Interface (SPI) Interface Protocol Register Structure Register Descriptions Vendor ID Register (Address 0x00) ADC Data Register (Address 0x01) ADC Sequence Register (Address 0x03) Configuration Register Bank (Address 0x05) Digital Output Driver Subregister (Address 0x01) Digital I/O Function Subregister (Address 0x02) General Subregister (Address 0x08) VIN RANGE0 and VIN RANGE1 Subregisters (Address 0x10 and Address 0x11) ADC Sampling Mode Subregister (Address 0x12) VIN Filter Subregister (Address 0x13) Conversion Delay Control Subregister (Address 0x14) VIN ALERT0 Routing and VIN ALERT1 Routing Subregisters (Address 0x15 and Address 0x16) Temperature Sensor Subregister (Address 0x20) Temperature Sensor Alert Routing Subregister (Address 0x21) GPIO2/DAC DISABLE0 and GPIO4/DAC DISABLE1 Subregisters (Address 0x30 and Address 0x31) Alert Limits Register Bank (Address 0x06) Alert High Limit and Alert Low Limit Subregisters Hysteresis Subregisters Alert Flags Register Bank (Address 0x07) ADC Alert Flags and TSENSE Alert Flags Subregisters (Address 0x00 and Address 0x02) Minimum and Maximum Register Bank (Address 0x08) Offset Register Bank (Address 0x09) DAC Buffer Enable Register (Address 0x0A) GPIO Register (Address 0x0B) Conversion Command Register (Address 0x0E) ADC Conversion Result Registers, VIN0 to VIN7 (Address 0x10 to Address 0x17) TSENSE Conversion Result Register (Address 0x20) DAC Channel Registers (Address 0x30 to Address 0x33) ADC Conversion Control ADC Conversion Command ADC Sequencer DAC Output Control LDAC Operation Simultaneous Update of All DAC Outputs Alerts and Limits Alert Limit Monitoring Features Hysteresis Hardware Alert Pins Alert Flag Bits in the Conversion Result Registers Alert Flags Register Bank Minimum and Maximum Conversion Results Outline Dimensions Ordering Guide