Datasheet AD74412R (Analog Devices) - 31

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Data Sheet AD74412R Voltage Input Mode Interpreting ADC Data
In voltage input mode, the voltage across the screw terminals In voltage input mode, the ADC, by default, is configured to (I/OP_x to I/ON_x) is measured by the ADC via the SENSELF_x measure the voltage across the screw terminals (I/OP_x to and the AGND_SENSE pins. It is essential to connect the AGND_ I/ON_x) in a 0 V to 10 V range. Use the ADC measurement SENSE pin as close as possible to the I/ON_x screw terminal to result to calculate the voltage across these screw terminals by ensure an accurate voltage measurement. Figure 37 shows the using the following equation: current and measurement paths of the voltage input mode. VADC = VMIN + (ADC_CODE/65,535) × Voltage Range
Selectable 200 kΩ to GND
where: In voltage input mode, there is an option to connect the VMIN is the minimum input voltage of the selected ADC range VIOUTN_x pins to ground via a 200 kΩ resistor, which is and is 0 V by default. enabled via the ADC_CONFIGx registers (disabled by default). VADC is the measured voltage in volts. This option is useful if there is a discrepancy in the ADC ADC_CODE is value of the ADC_RESULTx registers. measurement of the I/OP_x screw terminals, such as floating Voltage Range is the measurement range of the ADC and is 10 V. voltages. By enabling the 200 kΩ resistor, a small current is drawn through the 200 kΩ resistor, which pul s the voltage to ground.
REFOUT REFIN ALDO1V8 ALDO5V AVDD MEASUREMENT PATH CURRENT PATH AD74412R 1.8V 5V ALDO ALDO IOVDD CCOMP_x DVCC VIOUTP_x 1nF CASCODE_x DLDO1V8 1.8V 2.5V INTERNAL DLDO VREF OSCILLATOR R DAC 200kΩ SENSE 100, 0.1% 10ppm/°C I/OP_x DGND BAV99 SCLK SENSEHF_x SYNC L SENSELF_x UX VIOUTN_x SDI ADC UX M AGND_SENSE M SDO SENSEH_x 2kΩ, 0.1% CHANNE INPUT ALERT SHIFT SENSEHF_x REGISTER ADC_RDY C VOLTAGE R LOAD AND C FILTER FILTER SOURCE 68nF DIGITAL LDAC DIAGNOSTICS SENSELF_x LOGIC BLOCK SENSEL_x 2kΩ GPO_A UX 0V M SENSEL_x TO GPO_B SENSELF_x TVS 10V R GPO_C C FILTER FILTER THRESHOLD GPO_D CHANNEL A POWER-ON CHANNEL B RESET RESET I/ON_x CHANNEL C AVSS = NEGATIVE DVCC CHARGE PUMP AGND CHANNEL D AGND1 AVSS CPUMP_N CPUMP_P AGND3 AGND2 AGND_SENSE
008
CPUMP FLY
21274-
CAPACITOR
Figure 37. Voltage Input Mode Configuration Rev. A | Page 31 of 66 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION COMPANION PRODUCTS PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS VOLTAGE OUTPUT CURRENT OUTPUT VOLTAGE INPUT CURRENT INPUT EXTERNALLY POWERED CURRENT INPUT LOOP POWERED RTD MEASUREMENT DIGITAL INPUT LOGIC DIGITAL INPUT LOOP POWERED ADC SPECIFICATIONS GENERAL SPECIFICATIONS TIMING CHARACTERISTICS SPI Timing Specifications Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS VOLTAGE OUTPUT CURRENT OUTPUT REFERENCE ADC SUPPLIES THEORY OF OPERATION ROBUST ARCHITECTURE SERIAL INTERFACE DAC ARCHITECTURE ADC OVERVIEW REFERENCE Reference Noise Charge Pump POWER-ON STATE OF THE AD74412R DEVICE FUNCTIONS High Impedance Interpreting ADC Data Voltage Output Mode Voltage Output Short-Circuit Protection Interpretin ADC Data Current Output Mode Current Output Open Circuit Detection Interpreting ADC Data Voltage Input Mode Selectable 200 kΩ to GND Interpreting ADC Data Current Input, Externally Powered Mode Short-Circuit Protection Interpreting ADC Data Current Input, Loop Powered Mode Short-Circuit Protection Interpreting ADC Data Resistance Measurement (External 2-Wire RTD) Interpreting ADC Data Digital Input Logic Interpreting ADC Data Digital Input Current Sink Digital Input Threshold Setting Debounce Function Debounce Mode 0 (Default) Debounce Mode 1 Digital Input Inverter DIGITAL INPUT, LOOP POWERED MODE Interpreting ADC Data GETTING STARTED USING CHANNEL FUNCTIONS Switching Channel Functions ADC FUNCTIONALITY ADC Conversion Rates ADC_RDYB Functionality ADC Output Data Format ADC Noise DIAGNOSTICS DACs LDAC Function Clear Code Function Digital Linear Slew Rate Control DRIVING INDUCTIVE LOADS RESET FUNCTION THERMAL ALERT AND THERMAL RESET FAULTS AND ALERTS Channel Faults POWER SUPPLY MONITORS GPO_x PINS SPI INTERFACE AND DIAGNOSTICS SPI CRC SPI Interface SCLK Count Feature Readback Mode Streaming Mode Auto Readback BOARD DESIGN AND LAYOUT CONSIDERATIONS APPLICATIONS INFORMATION REGISTER MAP NOP REGISTER FUNCTION SETUP REGISTER PER CHANNEL ADC CONFIGURATION REGISTER PER CHANNEL DIGITAL INPUT CONFIGURATION REGISTER PER CHANNEL GPO PARALLEL DATA REGISTER GPO CONFIGURATION REGISTER PER CHANNEL OUTPUT CONFIGURATION REGISTER PER CHANNEL DAC CODE REGISTER PER CHANNEL DAC CLEAR CODE REGISTER PER CHANNEL DAC ACTIVE CODE REGISTER PER CHANNEL DIGITAL INPUT THRESHOLD REGISTER ADC CONVERSION CONTROL REGISTER DIAGNOSTICS SELECT REGISTER DIGITAL OUTPUT LEVEL REGISTER ADC CONVERSION RESULTS REGISTER PER CHANNEL DIAGNOSTIC RESULTS REGISTERS PER DIAGNOSTIC CHANNEL ALERT STATUS REGISTER LIVE STATUS REGISTER ALERT MASK REGISTER READBACK SELECT REGISTER 80 SPS ADC CONVERSION CONTROL REGISTER THERMAL RESET ENABLE REGISTER COMMAND REGISTER SCRATCH OR SPARE REGISTER SILICON REVISION REGISTER OUTLINE DIMENSIONS ORDERING GUIDE