Datasheet LT3753 (Analog Devices) - 10

LT3753
PIN FUNCTIONS TEST1 (Pin 1):
Connect to GND.
SS2 (Pin 17):
Capacitor controls soft-start of COMP pin.
NC (Pins 2, 15, 16, 34, 37):
No Connect Pins. These Alternatively can connect to OPTO to communicate start of pins are not connected inside the IC. These pins should switching to secondary side. If unused, leave the pin open. be left open.
GND (Pin 18):
Analog Signal Ground. Electrical connection
RT (Pin 3):
A resistor to ground programs switching exists inside the IC to the exposed pad (Pin 39). frequency.
PGND (Pins 19, 38, 39):
The Power Grounds for the IC.
FB (Pin 4):
Error Amplifier Inverting Input. The package has an exposed pad (Pin 39) underneath the IC which is the best path for heat out of the package. Pin 39
COMP (Pin 5):
Error Amplifier Output. Allows various should be soldered to a continuous copper ground plane compensation networks for nonisolated applications. under the device to reduce die temperature and increase
SYNC (Pin 6):
Allows synchronization of internal oscillator the power capability of the LT3753. to an external clock. fSYNC equal to fOSC allowed.
ISENSEN (Pin 20):
Negative input for the current sense
SS1 (Pin 7):
Capacitor controls soft-start/stop of switch- comparator. Kelvin connect to the sense resistor in the ing frequency and volt-second clamp. During soft-stop it source of the power MOSFET. also controls the COMP pin.
ISENSEP (Pin 21):
Positive input for the current sense
IVSEC (Pin 8):
Resistor Programs OUT Pin Maximum comparator. Kelvin connect to the sense resistor in the Duty Cycle Clamp (D source of the power MOSFET. A resistor in series with VSEC). This clamp moves inversely proportional to system input voltage to provide a volt- ISENSEP programs slope compensation. second clamp.
OC (Pin 22):
An accurate 96mV threshold, independent
UVLO_V
of duty cycle, for detection of primary side MOSFET over-
SEC (Pin 9):
A resistor divider from system in- put allows switch maximum duty cycle to vary inversely current and trigger of hiccup mode. Connect directly to proportional with system input. This volt-second clamp sense resistor in the source of the primary side MOSFET. prevents transformer saturation for duty cycles above
Missing Pins 23, 25, 27, 29, 31, 33, 35:
Pins removed 50%. Resistor divider ratio programs undervoltage lockout for high voltage spacings and improved reliability. (UVLO) threshold. A 5µA pin current hysteresis allows programming of UVLO hysteresis. Pin below 0.4V reduces
OUT (Pin 24):
Drives the gate of an N-channel MOSFET V between 0V and INTVCC. Active pull-off exists in shutdown. IN currents to microamps.
OVLO (Pin 10):
A resistor divider from system input
INTVCC (Pin 26):
A linear regulator supply generated from programs overvoltage lockout (OVLO) threshold. Fixed VIN. Supplies 10V for AOUT, SOUT and OUT gate drivers. hysteresis included. INTVCC must be bypassed with a 4.7µF capacitor to power ground. Can be externally driven by the housekeeping
TAO (Pin 11):
A resistor programs nonoverlap timing supply to remove power from within the IC. between AOUT rise and OUT rise control signals.
VIN (Pin 28):
Input Supply Pin. Bypass with 1µF to ground.
TAS (Pin 12):
Resistors at TAO and TAS define delay between SOUT fall and OUT rise (= t
SOUT (Pin 30):
Sync signal for secondary side synchro- AO – tAS). nous rectifier controller.
TOS (Pin 13):
Resistor programs delay between OUT fall and SOUT rise.
AOUT (Pin 32):
Control signal for external active clamp switch.
TBLNK (Pin 14):
Resistor programs extended blanking of I
TEST2 (Pin 36):
Connect to GND. SENSEP and OC signals during MOSFET turn-on. Rev. B 10 For more information www.analog.com Document Outline Features Applications Typical Application Description Table of Contents Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagrams Operation Applications Information Package Description Revision History Typical Application Related Parts