Datasheet ADP1032 (Analog Devices) - 6

ADP1032 Data Sheet Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Channel Matching Codirectional tPSKCD 0.5 5.5 ns Opposing Direction tPSKOD 0.5 4 ns Propagation Delay tPHL, tPLH 50% input to 50% output 7 11 ns VMVDD = 5 V, VSVDD1 = 5 V 7 12 ns VMVDD = 3.3 V, VSVDD1 = 5 V 7 15 ns VMVDD = 3.3 V, VSVDD1 = 3.3 V 8.5 12 ns VMVDD = 2.3 V, VSVDD1 = 1.8 V Jitter 620 ps p-p VMVDD = 5 V, VSVDD1 = 5 V 100 ps rms VMVDD = 5 V, VSVDD1 = 5 V 440 ps p-p VMVDD = 3.3 V, VSVDD1 = 5 V 80 ps rms VMVDD = 3.3 V, VSVDD1 = 5 V 290 ps p-p VMVDD = 3.3 V, VSVDD1 = 3.3 V 60 ps rms VMVDD = 3.3 V, VSVDD1 = 3.3 V 410 ps p-p VMVDD = 2.3 V, VSVDD1 = 1.8 V 110 ps rms VMVDD = 2.3 V, VSVDD1 = 1.8 V MGPI1, MGPI2, SGPI3 Data Rate 100 kbps Input Pulse Width tPW 10 μs Within PWD limit Propagation Delay tPHL, tPLH 14 μs 50% input to 50% output Jitter 19.5 μs ISOLATORS AC SPECIFICATIONS General-Purpose Input/Output (GPIO) Output Rise Time/Fall Time tR/tF 2.5 ns 10% to 90% SPI Output Rise Time/Fall Time tR/tF 2 ns 10% to 90% Common-Mode Transient |CM| 100 kV/μs Immunity7 1 VIx is the Channel x logic input, where Channel x can be MCK, MO, SO, MGPI1, MGPI2, or SGPI3. 2 VxVDD = VMVDD or VSVDDx. In these places, either VMVDD or VSVDDx can be used. 3 IOx is the output current of the pin. 4 VIXH is the input side, logic high. 5 VIXL is the input side, logic low. 6 VOX is the voltage where the output is pulled. 7 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VOUT > 0.8 MVDD and/or SVDDx. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. Rev. 0 | Page 6 of 37 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TYPICAL APPLICATION CIRCUIT COMPANION PRODUCTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS REGULATORY INFORMATION ELECTROMAGNECTIC COMPATIBILITY INSULATION AND SAFETY RELATED SPECIFICATIONS DIN V VDE 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION FLYBACK REGULATOR Flyback Regulator Operation Power Saving Mode (PSM) Flyback Undervoltage Lockout (UVLO) Flyback Regulator Precision Enable Control Flyback Regulator Soft Start Flyback Slew Rate Control Flyback Regulator Overcurrent Protection Flyback Regulator Overvoltage Protection BUCK REGULATOR Buck Regulator Operation Buck Regulator UVLO Buck Regulator Soft Start Buck Regulator Current-Limit Protection Buck Regulator Active Pull-Down Resistor Buck Regulator OVP POWER GOOD POWER-UP SEQUENCE OSCILLATOR AND SYNCHRONIZATION THERMAL SHUTDOWN DATA ISOLATION High Speed SPI Channels GPIO Data Channels APPLICATIONS INFORMATION COMPONENT SELECTION Feedback Resistors Capacitor Selection FLYBACK REGULATOR COMPONENTS SELECTION Input Capacitor Output Capacitor Ripple Current vs. Capacitor Value Schottky Diode Transformer Turn Ratio Primary Inductance Flyback Transformer Saturation Current Series Winding Resistance Leakage Inductance and Clamping Circuits Clamping Resistor Clamping Capacitor Clamping Diode Diode, Zener Diode Clamp Ripple Current (IAC) vs. Inductance Maximum Output Current Calculation BUCK REGULATOR COMPONENTS SELECTION Inductor Output Capacitor INSULATION LIFETIME Surface Tracking Insulation Wear Out Calculation and Use of Parameters Example THERMAL ANALYSIS TYPICAL APPLICATION CIRCUIT PCB LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE