Datasheet AD2420(W), AD2426(W), AD2427(W), AD2428(W), AD2429(W) (Analog Devices) - 5

AD2420(W) / AD2426(W) / AD2427(W) /AD2428(W) / AD2429(W) SUPERFRAME: 20.83ȝs FOR 48kHz SAMPLING RATE SYNCH SYNCH SYNCH DOWNSTREAM UPSTREAM CONTROL RESPONSE CONTROL A2B DATA SLOTS A2B DATA SLOTS FRAME FRAME FRAME
Figure 3. A2B Superframe
MASTER NODE I2S TX DATA I2S UPSTREAM DATA N - 2 I2S UPSTREAM DATA N - 1 I2S UPSTREAM DATA N I2S RX I2S DOWNSTREAM DATA M I2S DOWNSTREAM DATA M + 1 I2S DOWNSTREAM DATA M + 2 DATA SUPERFRAME DNSTREAM UPSTREAM DNSTREAM UPSTREAM DNSTREAM UPSTREAM A2B DATA A2B DATA A2B DATA A2B DATA A2B DATA A2B DATA A2B DATA SCF SCF M-1 SRF N-1 SCF M SRF N SCF M+1 SRF N+1 SLAVE NODE I2S RX I2S UPSTREAM DATA N I2S UPSTREAM DATA N + 1 I2S UPSTREAM DATA N + 2 DATA I2S TX I2S DOWNSTREAM DATA M - 2 I2S DOWNSTREAM DATA M - 1 I2S DOWNSTREAM DATA M DATA
Figure 4. A2B Bus Synchronous Data Exchange
I2C INTERFACE
BUS_ADDR (Bit 1 = 1) to access a bus node slave transceiver through a master configured AD2425W transceiver. See the The I2C interface in the transceiver provides access to the inter- AD2420(W)/6(W)/7(W)/8(W)/9(W) Automotive Audio Bus A2B nal registers. Operation is not guaranteed above the VI2C_VBUS Transceiver Technical Reference for details. specification. The I2C interface has the following features: • Slave functionality in the A2B master
I2S/TDM INTERFACE
• Master or slave functionality in the A2B slave The I2S/TDM serial port operates in full-duplex mode, where both the transmitter and receiver operate simultaneously using • Multimaster support in the A2B slave the same critical timing bit clock (BCLK) and synchronization • 100 kbps or 400 kbps rate operation (SYNC) pins. A2B slave transceivers generate the timing signals • 7-bit addressing on the BCLK and SYNC output pins. A2B master transceivers use the same BCLK and SYNC pins as inputs, which are driven • Single-word and burst mode read and write operations by the host device. The I2S/TDM port includes the following • Clock stretching features: All transceivers can be accessed by a locally connected processor • Programmable clock and frame sync timing and polarity using the 7-bit I2C device address (BASE_ADDR) established by • Numerous TDM operating modes the logic levels applied to the ADR2/IO2 and ADR1/IO1 pins at power-on reset, thus providing for up to four master devices • 16- or 32-bit data width connecting to the same I2C bus. A slave configured transceiver • Simultaneous operation with PDM port recognizes only this I2C device address. A master configured • Single- or dual-pin input/output (I/O) transceiver, however, also recognizes a second I2C device address for remote access to slave nodes over the A2B bus (BUS_ADDR). The least significant bit (LSB) of the 7-bit device address determines whether an I2C data exchange uses the BASE_ADDR (Bit 1 = 0) to access the transceiver or Rev. B | Page 5 of 38 | January 2020 Document Outline Automotive Audio Bus A2B Transceiver A2B Bus Features A2B Transceiver Features Applications Table of Contents Revision History General Description A2B Bus Details I2C Interface I2S/TDM Interface I2S Reduced Rate Pulse Density Modulation (PDM) Interface GPIO Over Distance Mailboxes Data Slot Exchange Between Slaves Clock Sustain State Programmable Settings to Optimize EMC Performance Programmable LVDS Transmit Levels Spread-Spectrum Clocking Unique ID Support for Crossover or Straight Through Cabling Data Only and Power Only Bus Operation Specifications Operating Conditions Electrical Characteristics Power Supply Rejection Ratio (PSRR) Timing Specifications Power-Up Sequencing Restrictions A2B Bus System Specification RMS Time Interval Error (TIE) Jitter PDM Typical Performance Characteristics Absolute Maximum Ratings Thermal Characteristics ESD Caution Test Circuits and Switching Characteristics Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Capacitive Loading Pin Configuration and Function Descriptions Power Analysis Current Flow Constant Current PLL Supply Current VIN Quiescent Current IOVDD Current Peripheral Supply Current Digital Logic Supply Current A2B Bus TX/RX Current LVDS Transmitter and Receiver Supply Currents Downstream/Upstream Activity Level LVDS Transmitter and Receiver Idle Current VREG1 and VREG2 Output Currents Current at VIN (IVIN) Power Dissipation Resistance Between Nodes Voltage Regulator Current in Master Node or Local Powered Slave Node Power Dissipation of A2B Bus Power Analysis of Bus Powered System Supply Voltage Reducing Power Consumption Power-Down Mode Standby Mode Control Mode Thermal Power Designer Reference VSENSE and Considerations for Diodes Optional Add On Circuits Layout Guidelines Outline Dimensions Automotive Products Ordering Guide