Datasheet KSZ8993M (Microchip) - 8

KSZ8993M TABLE 2-1: SIGNALS (CONTINUED) Pin Pin Name Type Description Number
1 = Port 1 default to full duplex mode if P1ANEN = 1 and auto negotia- tion fails. Force port 1 in full-duplex mode if P1ANEN = 0. 32 P1DPX IPD 0 = Port 1 default to half duplex mode if P1ANEN = 1 and auto negotia- tion fails. Force port 1 in half duplex mode if P1ANEN = 0. 1 = Always enable (force) port 1 flow control feature 33 P1FFC IPD 0 = Port 1 flow control feature enable is determined by auto negotiation result. 34 NC IPD No connect 35 NC IPD No connect 36 PWRDN IPU Chip power-down input (active-low) 37 AGND GND Analog ground 38 VDDA P 1.8V analog VDD 39 AGND GND Analog ground 40 MUX1 I Factory test pin - float for normal operation 41 MUX2 I Factory test pin - float for normal operation 42 AGND GND Analog ground 43 VDDA P 1.8V analog VDD 44 FXSD1 I Fiber signal detect/factory test pin 45 RXP1 I/O Physical receive or transmit signal (+ differential) 46 RXM1 I/O Physical receive or transmit signal (– differential) 47 AGND GND Analog ground 48 TXP1 I/O Physical transmit or receive signal (+ differential) 49 TXM1 I/O Physical transmit or receive signal (– differential) 50 VDDATX P 3.3V analog VDD 51 VDDARX P 3.3V analog VDD 52 RXM2 I/O Physical receive or transmit signal (– differential) 53 RXP2 I/O Physical receive or transmit signal (+ differential) 54 AGND GND Analog ground 55 TXM2 I/O Physical transmit or receive signal (– differential) 56 TXP2 I/O Physical transmit or receive signal (+ differential) 57 VDDA P 1.8V analog VDD 58 AGND GND Analog ground 59 TEST1 I Factory test pin - float for normal operation 60 TEST2 IPU Factory test pin - float or pull-up for normal operation Set physical transmit output current. 61 ISET O Pull-down this pin with a 3.01 kΩ 1% resistor to ground. 62 AGND GND Analog ground 63 VDDAP P 1.8V analog VDD for PLL 64 AGND GND Analog ground 65 X1 I 25 MHz crystal/oscillator clock connections Pins (X1, X2) connect to a crystal. If an oscillator is used, X1 connects to 66 X2 O a 3.3V tolerant oscillator and X2 is a no connect.
Note:
Clock is ±50 ppm for both crystal and oscillator. 67 RST_N IPU Hardware reset pin (active-low) DS00003066A-page 8  2019 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 MAC and Switch 3.3 Advanced Switch Functions 3.4 Configuration Interface 3.5 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Register Map: Switch and PHY (8-bit registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-127) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 SNI Timing 7.3 MAC Mode MII Timing 7.4 PHY Mode MII Timing 7.5 SPI Timing 7.6 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline 10.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Website Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service