Datasheet KSZ8993M (Microchip) - 5

HerstellerMicrochip
BeschreibungIntegrated 3-Port 10/100 Managed Switch with PHYs
Seiten / Seite74 / 5 — KSZ8993M. 2.0. PIN DESCRIPTION AND CONFIGURATION. FIGURE 2-1:. 128-PIN …
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KSZ8993M. 2.0. PIN DESCRIPTION AND CONFIGURATION. FIGURE 2-1:. 128-PIN PQFP ASSIGNMENT, (TOP VIEW)

KSZ8993M 2.0 PIN DESCRIPTION AND CONFIGURATION FIGURE 2-1: 128-PIN PQFP ASSIGNMENT, (TOP VIEW)

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KSZ8993M 2.0 PIN DESCRIPTION AND CONFIGURATION FIGURE 2-1: 128-PIN PQFP ASSIGNMENT, (TOP VIEW)
PV31 PS0 PS1 SPIS_N SDA SCL SPIQ MDIO MDC PRSEL0 PRSEL1 VDDC DGND SCONF0 SCONF1 SCRS SCOL SMRXD0 SMRXD1 SMRXD2 SMRXD3 SMRXDV SMRXC VDDIO DGND SMTXC SMTXER SMTXD0 SMTXD1 SMTXD2 SMTXD3 SMTXEN LEDSEL0 SMAC BPEN RST_N X2 X1 65 103 AGND PV32 VDDAP PV21 AGND PV23 ISET DGND TEST2 VDDIO TEST1 PV12 AGND PV13 VDDA P3_1PEN TXP2 P2_1PEN TXM2 P1_1PEN AGND P3_TXQ2 RXP2 P2_TXQ2 RXM2 P1_TXQ2 VDDARX P3_PP VDDATX P2_PP TXM1 P1_PP TXP1 P3_TAGINS AGND P2_TAGINS RXM1 P1_TAGINS RXP1 DGND FXSD1 VDDC VDDA P3_TAGRM AGND P2_TAGRM MUX2 P1_TAGRM MUX1 TESTEN SCANEN 39 AGND 1 NC NC NC NC NC NC NC NC NC NC DGND VDDIO DGND VDDC AGND VDDA P1LED2 P1LED1 P1LED0 P2LED2 P2LED1 P2LED0 ADVFC P2SPD P2DPX P3FFC P1SPD P1DPX P1FFC P2ANEN P2LED3 P1LED3 P2MDIX PWRDN LEDSEL1 P1ANEN HWPOVR P2MDIXDIS  2019 Microchip Technology Inc. DS00003066A-page 5 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 MAC and Switch 3.3 Advanced Switch Functions 3.4 Configuration Interface 3.5 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Register Map: Switch and PHY (8-bit registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-127) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 SNI Timing 7.3 MAC Mode MII Timing 7.4 PHY Mode MII Timing 7.5 SPI Timing 7.6 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline 10.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Website Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service