Datasheet KSZ8895MQX, KSZ8895RQX KSZ8895FQX, KSZ8895MLX (Microchip)

KSZ8895MQX/RQX/FQX/MLX Integrated 5-Port 10/100 Managed Ethernet Switch with MII/RMII Interface Features
• Programmable Weighted Fair Queuing for Ratio Control
Advanced Switch Features
• Re-Mapping of 802.1p Priority Field Per Port • IEEE 802.1q VLAN Support for up to 128 Active Basis VLAN Groups (Full-Range 4096 of VLAN IDs)
Integrated 5-Port 10/100 Ethernet Switch
• Static MAC Table Supports up to 32 Entries • New Generation Switch with Five MACs and Five • VLAN ID Tag/Untagged Options, Per Port Basis PHYs that are Fully Compliant with the IEEE • IEEE 802.1p/q Tag Insertion or Removal on a Per 802.3u Standard Port Basis Based on Ingress Port (Egress) • PHYs Designed with Patented Enhanced Mixed- • Programmable Rate Limiting at the Ingress and Signal Technology Egress on a Per Port Basis • Non-Blocking Switch Fabric Ensures Fast Packet • Jitter-Free Per Packet Based Rate Limiting Sup- Delivery by Utilizing a 1K MAC Address Lookup port Table and a Store-and-Forward Architecture • Broadcast Storm Protection with Percentage Con- • On-Chip 64Kbyte Memory for Frame Buffering trol (Global and Per Port Basis) (Not Shared with 1K Unicast Address Table) • IEEE 802.1d Rapid Spanning Tree Protocol • Full-Duplex IEEE 802.3x Flow Control (PAUSE) RSTP Support with Force Mode Option • Tail Tag Mode (1 Byte Added Before FCS) Sup- • Half-Duplex Back Pressure Flow Control port at Port 5 to Inform the Processor Which • HP Auto MDI/MDI-X and IEEE Auto Crossover Ingress Port Receives the Packet Support • 1.4 Gbps High-Performance Memory Bandwidth • SW-MII Interface Supports Both MAC Mode and and Shared Memory Based Switch Fabric with PHY Mode Fully Non-Blocking Configuration • 7-Wire Serial Network Interface (SNI) Support for • Dual MII with MAC 5 and PHY 5 on Port 5, SW5- Legacy MAC MII/RMII for MAC 5 and P5-MII/RMII for PHY 5 • Per Port LED Indicators for Link, Activity, and 10/ • Enable/Disable Option for Huge Frame Size up to 100 Speed 2000 Bytes Per Frame • Register Port Status Support for Link, Activity, • IGMP v1/v2 Snooping (IPv4) Support for Multicast Full-/Half-Duplex and 10/100 Speed Packet Filtering • LinkMD® Cable Diagnostic Capabilities • IPv4/IPv6 QoS Support • On-Chip Terminations and Internal Biasing Tech- • Support Unknown Unicast/Multicast Address and nology for Cost Down and Lowest Power Con- Unknown VID Packet Filtering sumption • Self-Address Filtering
Switch Monitoring Features Comprehensive Configuration Register Access
• Port Mirroring/Monitoring/Sniffing: Ingress and/or • Serial Management Interface (MDC/MDIO) to All Egress Traffic to Any Port or MII PHYs Registers and SMI Interface (MDC/MDIO) • MIB Counters for Fully Compliant Statistics Gath- to All Registers ering; 34 MIB Counters Per Port • High-Speed SPI (up to 25 MHz) and I2C Master • Loopback Support for MAC, PHY, and Remote Interface to all Internal Registers Diagnostic of Failure • I/O Pins Strapping and EEPROM to Program • Interrupt for the Link Change on Any Ports Selective Registers in Unmanaged Switch Mode • Control Registers Configurable on the Fly (Port-
Low-Power Dissipation
Priority, 802.1p/d/q, AN…) • Full-Chip Hardware Power-Down
QoS/CoS Packet Prioritization Support
• Full-Chip Software Power-Down and Per Port Software Power-Down • Per Port, 802.1p and DiffServ-Based • Energy-Detect Mode Support <100 mW Full-Chip • 1/2/4-Queue QoS Prioritization Selection Power Consumption When All Ports Have No  2016 - 2019 Microchip Technology Inc. DS00002246B-page 1 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 Power 3.3 Power Management 3.4 Switch Core 3.5 Advanced Functionality 3.6 MII Management (MIIM) Interface 3.7 Serial Management Interface (SMI) 4.0 Register Descriptions 4.1 Global Registers 4.2 Port Registers 4.3 Advanced Control Registers 4.4 Static MAC Address Table 4.5 VLAN Table 4.6 Dynamic MAC Address Table 4.7 Management Information Base (MIB) Counters 4.8 MIIM Registers 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings*** 6.0 Electrical Characteristics 7.0 Timing Diagrams 7.1 EEPROM Timing 7.2 SNI Timing 7.3 MII Timing 7.4 RMII Timing 7.5 SPI Timing 7.6 Auto-Negotiation Timing 7.7 MDC/MDIO Timing 7.8 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformer, (Note 9-1) 10.0 Package Outline Appendix A: Data Sheet Revision History The Microchip Website Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service