Datasheet KSZ8873MML (Microchip) - 9
| Hersteller | Microchip |
| Beschreibung | Integrated 3-Port 10/100 Managed Switch with PHY |
| Seiten / Seite | 91 / 9 — KSZ8873MML. TABLE 2-1:. SIGNALS (CONTINUED). Type. Pin. Note. … |
| Dateiformat / Größe | PDF / 1.3 Mb |
| Dokumentensprache | Englisch |
KSZ8873MML. TABLE 2-1:. SIGNALS (CONTINUED). Type. Pin. Note. Description. Number. Name. 2-1. Port 2 LED Indicators:. Strap option:
Modelllinie für dieses Datenblatt
Textversion des Dokuments
KSZ8873MML TABLE 2-1: SIGNALS (CONTINUED) Type Pin Pin Note Description Number Name 2-1
Switch MII transmit clock (MII modes only) 56 SMTXC1 I/O Output in PHY MII mode Input in MAC MII. 3.3V, 2.5V, or 1.8V digital V 57 VDDIO P DD input power supply for IO with well decoupling capacitors. 58 GND GND Digital ground 1.8V core power voltage output (internal 1.8V LDO regulator output), this 1.8V output pin provides power to both VDDA_1.8 and VDDC input pins. 59 VDDCO P Note: Internally 1.8V LDO regulator input comes from VDDIO. Do not connect an external power supply to VDDCO pin. The ferrite bead is requested between analog and digital 1.8V core power. 60 SMTXEN1 I Switch MII transmit enable Port 1 LED Indicators: (Not used) Strap option: Port 3 flow control selection(P3FFC) 61 P1LED1 IPU/O PU = Always enable (force) port 3 flow control feature PD = Disable Port 1 LED Indicators: (Not used) Strap option: Port 3 duplex mode selection(P3DPX) 62 P1LED0 IPD/O PU = Port 3 set to half-duplex mode PD = Port 3 set to full-duplex mode (default)
Port 2 LED Indicators:
Default: Speed (refer to register 195 bit[5:4])
Strap option:
Serial bus configuration
Port 2 LED Indicators:
Default: Link/Act. (refer to register 195 bit[5:4])
Strap option:
Serial bus configuration Serial bus configuration pins to select mode of access to KSZ8873MML inter- nal registers.
[P2LED1, P2LED0] = [0, 0] — I2C master (EEPROM) mode
63 P2LED1 IPU/O (If EEPROM is not detected, the KSZ8873MML will be configured with the default values of its internal registers and the values of its strap-in pins.) I
nterface Signals Type Description
SPIQ O Not used (tri-stated) SCL O I2C clock SDA I/O I2C data I/O SPIS_N I Not used 2018 Microchip Technology Inc. DS00002776A-page 9 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 Power Management 3.3 MAC and Switch 3.4 Advanced Switch Functions 3.5 Spanning Tree Support 3.6 Rapid Spanning Tree Support 3.7 Tail Tagging Mode 3.8 IGMP Support 3.9 Port Mirroring Support 3.10 Rate Limiting Support 3.11 Unicast MAC Address Filtering 3.12 Configuration Interface 3.13 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Memory Map (8-Bit Registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-198) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 MAC Mode MII Timing 7.3 PHY Mode MII Timing 7.4 I2C Slave Mode Timing 7.5 SPI Timing 7.6 Auto-Negotiation Timing 7.7 MDC/MDIO Timing 7.8 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline 10.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service
Switch MII transmit clock (MII modes only) 56 SMTXC1 I/O Output in PHY MII mode Input in MAC MII. 3.3V, 2.5V, or 1.8V digital V 57 VDDIO P DD input power supply for IO with well decoupling capacitors. 58 GND GND Digital ground 1.8V core power voltage output (internal 1.8V LDO regulator output), this 1.8V output pin provides power to both VDDA_1.8 and VDDC input pins. 59 VDDCO P Note: Internally 1.8V LDO regulator input comes from VDDIO. Do not connect an external power supply to VDDCO pin. The ferrite bead is requested between analog and digital 1.8V core power. 60 SMTXEN1 I Switch MII transmit enable Port 1 LED Indicators: (Not used) Strap option: Port 3 flow control selection(P3FFC) 61 P1LED1 IPU/O PU = Always enable (force) port 3 flow control feature PD = Disable Port 1 LED Indicators: (Not used) Strap option: Port 3 duplex mode selection(P3DPX) 62 P1LED0 IPD/O PU = Port 3 set to half-duplex mode PD = Port 3 set to full-duplex mode (default)
Port 2 LED Indicators:
Default: Speed (refer to register 195 bit[5:4])
Strap option:
Serial bus configuration
Port 2 LED Indicators:
Default: Link/Act. (refer to register 195 bit[5:4])
Strap option:
Serial bus configuration Serial bus configuration pins to select mode of access to KSZ8873MML inter- nal registers.
[P2LED1, P2LED0] = [0, 0] — I2C master (EEPROM) mode
63 P2LED1 IPU/O (If EEPROM is not detected, the KSZ8873MML will be configured with the default values of its internal registers and the values of its strap-in pins.) I
nterface Signals Type Description
SPIQ O Not used (tri-stated) SCL O I2C clock SDA I/O I2C data I/O SPIS_N I Not used 2018 Microchip Technology Inc. DS00002776A-page 9 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 Power Management 3.3 MAC and Switch 3.4 Advanced Switch Functions 3.5 Spanning Tree Support 3.6 Rapid Spanning Tree Support 3.7 Tail Tagging Mode 3.8 IGMP Support 3.9 Port Mirroring Support 3.10 Rate Limiting Support 3.11 Unicast MAC Address Filtering 3.12 Configuration Interface 3.13 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Memory Map (8-Bit Registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-198) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 MAC Mode MII Timing 7.3 PHY Mode MII Timing 7.4 I2C Slave Mode Timing 7.5 SPI Timing 7.6 Auto-Negotiation Timing 7.7 MDC/MDIO Timing 7.8 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline 10.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service