Datasheet KSZ8462HLI, KSZ8462FHLI (Microchip) - 7

KSZ8462HLI/FHLI 1.2 General Description
The KSZ8462 EtherSynch® product line consists of IEEE 1588v2 enabled Ethernet switches, providing integrated com- munications and synchronization for a range of Industrial Ethernet applications. The KSZ8462 EtherSynch product line enables distributed, daisy-chained topologies preferred for Industrial Ethernet networks. Conventional centralized (i.e., star-wired) topologies are also supported for dual-homed, fault-tolerant arrangements. A flexible 8- or 16-bit general bus interface is provided for interfacing to an external host processor. The KSZ8462 devices incorporate the IEEE 1588v2 protocol. Sub-microsecond synchronization is available via the use of hardware-based time-stamping and transparent clocks making it the ideal solution for time synchronized Layer 2 com- munication in critical industrial applications. Extensive general purpose I/O (GPIO) capabilities are available to use with the IEEE 1588v2 PTP to efficiently and accurately interface to locally connected devices. Complementing the industry’s most-integrated IEEE 1588v2 device is a precision timing protocol (PTP) v2 software stack that has been pre-qualified with the KSZ84xx product family. The PTP stack has been optimized around the KSZ84xx chip architecture, and is available in source code format along with Microchip’s chip driver. The wire-speed, store-and-forward switching fabric provides a full complement of quality-of-service (QoS) and conges- tion control features optimized for real-time Ethernet. The KSZ8462 product line is built upon Microchip’s industry-leading Ethernet technology, with features designed to off- load host processing and streamline your overal design. • Wire-speed Ethernet switching fabric with extensive filtering • Two integrated 10/100BASE-TX PHY transceivers, featuring the industry’s lowest power consumption • Full-featured quality-of-service (QoS) support • Flexible management options that support common standard interfaces A robust assortment of power-management features including Energy Efficient Ethernet (EEE) have been designed in to satisfy energy efficient environments.
FIGURE 1-1: KSZ8462 TOP LEVEL ARCHITECTURE KSZ8462
PRECISION CLOCK PRECISION GPIO 10/100 MAC PHY AMPING HOST MAC INTERFACE IEEE 1588 10/100 TIMEST MAC PHY 10/100 SWITCH  2018 Microchip Technology Inc. DS00002641A-page 7 Document Outline 1.0 Introduction 1.1 General Terms and Conditions 1.2 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Direction Terminology 3.2 Physical (PHY) Block 3.3 Media Access Controller (MAC) Block 3.4 Switch Block 3.5 Queue Management Unit (QMU) 3.6 IEEE 1588 Precision Time Protocol (PTP) Block 3.7 General Purpose and IEEE 1588 Input/Output (GPIO) 3.8 Using the GPIO Pins with the Trigger Output Units 3.9 Using the GPIO Pins with the Time Stamp Input Units 3.10 Device Clocks 3.11 Power 3.12 Power Management 3.13 Interfaces 4.0 Register Descriptions 4.1 Register Map of CPU Accessible I/O Registers 4.2 Register Bit Definitions 4.3 Management Information Base (MIB) Counters 4.4 Static MAC Address Table 4.5 Dynamic MAC Address Table 4.6 VLAN Table 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 Host Interface Read/Write Timing 7.2 Auto-Negotiation Timing 7.3 Trigger Output Unit and Time Stamp Input Unit Timing 7.4 Serial EEPROM Interface Timing 7.5 Reset and Power Sequence Timing 7.6 Reset Circuit Guidelines 8.0 Reference Circuit: LED Strap-In Pins 9.0 Reference Clock: Connection and Selection 10.0 Selection of Isolation Transformers 11.0 Package Outline Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service