Preliminary Datasheet AVR128DA28, AVR128DA32, AVR128DA48, AVR128DA64 (Microchip) - 4

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AVR128DA28/32/48/64 Features
• AVR® CPU – Running at up to 24 MHz – Single-cycle I/O access – Two-level interrupt controller – Two-cycle hardware multiplier – Supply voltage range: 1.8V to 5.5V • Memories – 128 KB In-System self-programmable Flash memory – 512B EEPROM – 16 KB SRAM – 32B of user row in nonvolatile memory that can keep data during chip-erase and be programmed while the device is locked – Write/erase endurance • Flash 10,000 cycles • EEPROM 100,000 cycles – Data retention: 40 years at 55°C • System – Power-on Reset (POR) circuit – Brown-out Detector (BOD) – Clock options • High-Precision internal high-frequency Oscillator with selectable frequency up to 24 MHz (OSCHF) – Auto-tuning for improved internal oscillator accuracy • Internal PLL up to 48 MHz for high-frequency operation of Timer/Counter type D (PLL) • 32.768 kHz Ultra Low-Power internal oscillator (OSC32K) • 32.768 kHz external crystal oscillator (XOSC32K) • External clock input – Single-pin Unified Program and Debug Interface (UPDI) – Three sleep modes • Idle with all peripherals running for immediate wake-up • Standby – Configurable operation of selected peripherals • Power-Down with full data retention • Peripherals – Up to two 16-bit Timer/Counter type A (TCA) with a dedicated period register and three PWM channels – Up to five 16-bit Timer/Counter type B (TCB) with input capture and simple PWM functionality – One 12-bit Timer/Counter type D (TCD) optimized for power control – One 16-bit Real-Time Counter (RTC) running from external crystal or internal oscillator – Up to six USART with fractional baud rate generator, auto-baud, and start-of-frame detection – Two master/slave Serial Peripheral Interface (SPI) – Up to two Two-Wire Interface (TWI) with dual address match • Independent master and slave operation (Dual mode) • Philips I2C compatible • Standard mode (Sm, 100 kHz) • Fast mode (Fm, 400 kHz) • Fast mode plus (Fm+, 1 MHz) (1) – Event System for CPU independent and predictable inter-peripheral signaling – Configurable Custom Logic (CCL) with up to six programmable Look-up Tables (LUT) – One 12-bit differential 130 ksps Analog-to-Digital Converter (ADC) © 2020 Microchip Technology Inc.
Preliminary Datasheet
DS40002183A-page 4 Document Outline Introduction AVR-DA Family Overview 1. Memory Overview 2. Peripheral Overview Features Table of Contents 1. Block Diagram 2. Pinout 2.1. 28-Pin SPDIP, SSOP and SOIC 2.2. 32-Pin VQFN and TQFP 2.3. 48-Pin VQFN and TQFP 2.4. 64-Pin VQFN and TQFP 3. I/O Multiplexing and Considerations 3.1. I/O Multiplexing 4. Hardware Guidelines 4.1. General Guidelines 4.1.1. Special Consideration for VQFN Packages 4.2. Connection for Power Supply 4.2.1. Digital Power Supply 4.3. Connection for RESET 4.4. Connection for UPDI Programming 4.5. Connecting External Crystal Oscillators 4.6. Connection for External Voltage Reference 5. Conventions 5.1. Numerical Notation 5.2. Memory Size and Type 5.3. Frequency and Time 5.4. Registers and Bits 5.4.1. Addressing Registers from Header Files 5.5. ADC Parameter Definitions 6. AVR® CPU 6.1. Features 6.2. Overview 6.3. Architecture 6.3.1. Arithmetic Logic Unit (ALU) 6.3.1.1. Hardware Multiplier 6.4. Functional Description 6.4.1. Program Flow 6.4.2. Instruction Execution Timing 6.4.3. Status Register 6.4.4. Stack and Stack Pointer 6.4.5. Register File 6.4.5.1. The X-, Y-, and Z-Registers 6.4.5.2. Extended Pointers 6.4.5.2.1. Extended Program Memory Pointer 6.4.6. Configuration Change Protection (CCP) 6.4.6.1. Sequence for Write Operation to Configuration Change Protected I/O Registers 6.4.6.2. Sequence for Execution of Self-Programming 6.4.7. On-Chip Debug Capabilities 6.5. Register Summary 6.6. Register Description 6.6.1. Configuration Change Protection 6.6.2. Stack Pointer 6.6.3. Status Register 6.6.4. Extended Z-Pointer Register 7. Memories 7.1. Overview 7.2. Memory Map 7.3. In-System Reprogrammable Flash Program Memory 7.4. SRAM Data Memory 7.5. EEPROM Data Memory 7.6. SIGROW - Signature Row 7.6.1. Signature Row Summary 7.6.2. Signature Row Description 7.6.2.1. Device ID 7.6.2.2. Temperature Sensor Calibration n 7.6.2.3. Serial Number Byte n 7.7. USERROW - User Row 7.8. FUSE - Configuration and User Fuses 7.8.1. Fuse Summary 7.8.2. Fuse Description 7.8.2.1. Watchdog Configuration 7.8.2.2. Brown-out Detector Configuration 7.8.2.3. Oscillator Configuration 7.8.2.4. System Configuration 0 7.8.2.5. System Configuration 1 7.8.2.6. Code Size 7.8.2.7. Boot Size 7.9. LOCK - Memory Sections Access Protection 7.9.1. Lock Summary 7.9.2. Lock Description 7.9.2.1. Lock Key 7.10. I/O Memory 7.10.1. Single-Cycle I/O Registers 7.10.2. Extended I/O Registers 7.10.3. Accessing 16-bit Registers 7.10.4. Accessing 24-Bit Registers 8. Peripherals and Architecture 8.1. Peripheral Address Map 8.2. Interrupt Vector Mapping 8.3. SYSCFG - System Configuration 8.3.1. Register Summary 8.3.2. Register Description 8.3.2.1. Device Revision ID Register 9. GPR - General Purpose Registers 9.1. Register Summary 9.2. Register Description 9.2.1. General Purpose Register n 10. NVMCTRL - Nonvolatile Memory Controller 10.1. Features 10.2. Overview 10.2.1. Block Diagram 10.3. Functional Description 10.3.1. Memory Organization 10.3.1.1. Flash 10.3.1.2. EEPROM 10.3.1.3. Signature Row 10.3.1.4. User Row 10.3.1.5. Fuses 10.3.2. Memory Access 10.3.2.1. Read 10.3.2.2. Programming 10.3.2.3. Command Modes 10.3.2.3.1. Flash Write Mode 10.3.2.3.2. Flash Page Erase Mode 10.3.2.3.3. Flash Multi-Page Erase Mode 10.3.2.3.4. EEPROM Write Mode 10.3.2.3.5. EEPROM Erase/Write Mode 10.3.2.3.6. EEPROM Byte Erase Mode 10.3.2.3.7. EEPROM Multi-Byte Erase Mode 10.3.2.3.8. Chip Erase Command 10.3.2.3.9. EEPROM Erase Command 10.3.3. Preventing Flash/EEPROM Corruption 10.3.4. Interrupts 10.3.5. Sleep Mode Operation 10.3.6. Configuration Change Protection 10.4. Register Summary 10.5. Register Description 10.5.1. Control A 10.5.2. Control B 10.5.3. Status 10.5.4. Interrupt Control 10.5.5. Interrupt Flags 10.5.6. Data 10.5.7. Address 11. CLKCTRL - Clock Controller 11.1. Features 11.2. Overview 11.2.1. Block Diagram - CLKCTRL 11.2.2. Signal Description 11.3. Functional Description 11.3.1. Main Clock Selection and Prescaler 11.3.2. Main Clock After Reset 11.3.3. Clock Sources 11.3.3.1. Internal Oscillators 11.3.3.1.1. Internal High-Frequency Oscillator (OSCHF) 11.3.3.1.2. 32.768 kHz Oscillator (OSC32K) 11.3.3.2. External Clock Sources 11.3.3.2.1. 32.768 kHz Crystal Oscillator (XOSC32K) 11.3.3.2.2. External Clock (EXTCLK) 11.3.4. Phase-Locked Loop (PLL) 11.3.5. Auto-Tune 11.3.6. Sleep Mode Operation 11.3.7. Configuration Change Protection 11.4. Register Summary 11.5. Register Description 11.5.1. Main Clock Control A 11.5.2. Main Clock Control B 11.5.3. Main Clock Lock 11.5.4. Main Clock Status 11.5.5. Internal High-Frequency Oscillator Control A 11.5.6. Internal High-Frequency Oscillator Frequency Tune 11.5.7. PLL Control A 11.5.8. 32.768 kHz Oscillator Control A 11.5.9. 32.768 kHz Crystal Oscillator Control A 12. SLPCTRL - Sleep Controller 12.1. Features 12.2. Overview 12.2.1. Block Diagram 12.3. Functional Description 12.3.1. Initialization 12.3.2. Voltage Regulator Configuration 12.3.3. Operation 12.3.3.1. Sleep Modes 12.3.3.2. Wake-up Time 12.3.4. Debug Operation 12.4. Register Summary 12.5. Register Description 12.5.1. Control A 12.5.2. Voltage Regulator Control Register 13. RSTCTRL - Reset Controller 13.1. Features 13.2. Overview 13.2.1. Block Diagram 13.2.2. Signal Description 13.3. Functional Description 13.3.1. Initialization 13.3.2. Operation 13.3.2.1. Reset Sources 13.3.2.1.1. Power-on Reset (POR) 13.3.2.1.2. Brown-out Detector (BOD) Reset 13.3.2.1.3. External Reset (RESET) 13.3.2.1.4. Watchdog Timer (WDT) Reset 13.3.2.1.5. Software Reset (SWRST) 13.3.2.1.6. Universal Program Debug Interface (UPDI) Reset 13.3.2.1.7. Domains Affected By Reset 13.3.2.2. Reset Time 13.3.3. Sleep Mode Operation 13.3.4. Configuration Change Protection 13.4. Register Summary 13.5. Register Description 13.5.1. Reset Flag Register 13.5.2. Software Reset Register 14. CPUINT - CPU Interrupt Controller 14.1. Features 14.2. Overview 14.2.1. Block Diagram 14.3. Functional Description 14.3.1. Initialization 14.3.2. Operation 14.3.2.1. Enabling, Disabling and Resetting 14.3.2.2. Interrupt Vector Locations 14.3.2.3. Interrupt Response Time 14.3.2.4. Interrupt Priority 14.3.2.4.1. Non-Maskable Interrupts 14.3.2.4.2. High-Priority Interrupt 14.3.2.4.3. Normal-Priority Interrupts 14.3.2.4.3.1. Static Scheduling 14.3.2.4.3.2. Modified Static Scheduling 14.3.2.4.3.3. Round Robin Scheduling 14.3.2.5. Compact Vector Table 14.3.3. Debug Operation 14.3.4. Configuration Change Protection 14.4. Register Summary 14.5. Register Description 14.5.1. Control A 14.5.2. Status 14.5.3. Interrupt Priority Level 0 14.5.4. Interrupt Vector with Priority Level 1 15. EVSYS - Event System 15.1. Features 15.2. Overview 15.2.1. Block Diagram 15.2.2. Signal Description 15.3. Functional Description 15.3.1. Initialization 15.3.2. Operation 15.3.2.1. Event User Multiplexer Setup 15.3.2.2. Event System Channel 15.3.2.3. Event Generators 15.3.2.4. Event Users 15.3.2.5. Synchronization 15.3.2.6. Software Event 15.3.3. Sleep Mode Operation 15.3.4. Debug Operation 15.4. Register Summary 15.5. Register Description 15.5.1. Software Events 15.5.2. Channel n Generator Selection 15.5.3. User Channel MUX 16. PORTMUX - Port Multiplexer 16.1. Overview 16.2. Register Summary 16.3. Register Description 16.3.1. EVSYS Pin Position 16.3.2. CCL LUTn Pin Position 16.3.3. USARTn Pin Position 16.3.4. USARTn Pin Position 16.3.5. SPIn Pin Position 16.3.6. TWIn Pin Position 16.3.7. TCAn Pin Position 16.3.8. TCBn Pin Position 16.3.9. TCDn Pin Position 16.3.10. ACn Pin Position 16.3.11. ZCDn Pin Position 17. PORT - I/O Pin Configuration 17.1. Features 17.2. Overview 17.2.1. Block Diagram 17.2.2. Signal Description 17.3. Functional Description 17.3.1. Initialization 17.3.2. Operation 17.3.2.1. Basic Functions 17.3.2.2. Port Configuration 17.3.2.3. Pin Configuration 17.3.2.4. Multi-Pin Configuration 17.3.2.5. Virtual Ports 17.3.2.6. Peripheral Override 17.3.3. Interrupts 17.3.3.1. Asynchronous Sensing Pin Properties 17.3.4. Events 17.3.5. Sleep Mode Operation 17.3.6. Debug Operation 17.4. Register Summary - PORTx 17.5. Register Description - PORTx 17.5.1. Data Direction 17.5.2. Data Direction Set 17.5.3. Data Direction Clear 17.5.4. Data Direction Toggle 17.5.5. Output Value 17.5.6. Output Value Set 17.5.7. Output Value Clear 17.5.8. Output Value Toggle 17.5.9. Input Value 17.5.10. Interrupt Flags 17.5.11. Port Control 17.5.12. Multi-Pin Configuration 17.5.13. Multi-Pin Control Update Mask 17.5.14. Multi-Pin Control Set Mask 17.5.15. Multi-Pin Control Clear Mask 17.5.16. Pin n Control 17.6. Register Summary - VPORTx 17.7. Register Description - VPORTx 17.7.1. Data Direction 17.7.2. Output Value 17.7.3. Input Value 17.7.4. Interrupt Flags 18. BOD - Brown-out Detector 18.1. Features 18.2. Overview 18.2.1. Block Diagram 18.3. Functional Description 18.3.1. Initialization 18.3.2. Interrupts 18.3.3. Sleep Mode Operation 18.3.4. Configuration Change Protection 18.4. Register Summary 18.5. Register Description 18.5.1. Control A 18.5.2. Control B 18.5.3. VLM Control 18.5.4. Interrupt Control 18.5.5. VLM Interrupt Flags 18.5.6. VLM Status 19. VREF - Voltage Reference 19.1. Features 19.2. Overview 19.2.1. Block Diagram 19.3. Functional Description 19.3.1. Initialization 19.4. Register Summary 19.5. Register Description 19.5.1. ADC0 Reference 19.5.2. DAC0 Reference 19.5.3. Analog Comparator Reference 20. WDT - Watchdog Timer 20.1. Features 20.2. Overview 20.2.1. Block Diagram 20.3. Functional Description 20.3.1. Initialization 20.3.2. Clocks 20.3.3. Operation 20.3.3.1. Normal Mode 20.3.3.2. Window Mode 20.3.3.3. Preventing Unintentional Changes 20.3.4. Sleep Mode Operation 20.3.5. Debug Operation 20.3.6. Synchronization 20.3.7. Configuration Change Protection 20.4. Register Summary 20.5. Register Description 20.5.1. Control A 20.5.2. Status 21. TCA - 16-bit Timer/Counter Type A 21.1. Features 21.2. Overview 21.2.1. Block Diagram 21.2.2. Signal Description 21.3. Functional Description 21.3.1. Definitions 21.3.2. Initialization 21.3.3. Operation 21.3.3.1. Normal Operation 21.3.3.2. Double Buffering 21.3.3.3. Changing the Period 21.3.3.4. Compare Channel 21.3.3.4.1. Waveform Generation 21.3.3.4.2. Frequency (FRQ) Waveform Generation 21.3.3.4.3. Single-Slope PWM Generation 21.3.3.4.4. Dual-Slope PWM 21.3.3.4.5. Port Override for Waveform Generation 21.3.3.5. Timer/Counter Commands 21.3.3.6. Split Mode - Two 8-Bit Timer/Counters 21.3.4. Events 21.3.5. Interrupts 21.3.6. Sleep Mode Operation 21.4. Register Summary - Normal Mode 21.5. Register Description - Normal Mode 21.5.1. Control A 21.5.2. Control B - Normal Mode 21.5.3. Control C - Normal Mode 21.5.4. Control D 21.5.5. Control Register E Clear - Normal Mode 21.5.6. Control Register E Set - Normal Mode 21.5.7. Control Register F Clear 21.5.8. Control Register F Set 21.5.9. Event Control 21.5.10. Interrupt Control Register - Normal Mode 21.5.11. Interrupt Flag Register - Normal Mode 21.5.12. Debug Control Register 21.5.13. Temporary Bits for 16-Bit Access 21.5.14. Counter Register - Normal Mode 21.5.15. Period Register - Normal Mode 21.5.16. Compare n Register - Normal Mode 21.5.17. Period Buffer Register 21.5.18. Compare n Buffer Register 21.6. Register Summary - Split Mode 21.7. Register Description - Split Mode 21.7.1. Control A 21.7.2. Control B - Split Mode 21.7.3. Control C - Split Mode 21.7.4. Control D 21.7.5. Control Register E Clear - Split Mode 21.7.6. Control Register E Set - Split Mode 21.7.7. Interrupt Control Register - Split Mode 21.7.8. Interrupt Flag Register - Split Mode 21.7.9. Debug Control Register 21.7.10. Low Byte Timer Counter Register - Split Mode 21.7.11. High Byte Timer Counter Register - Split Mode 21.7.12. Low Byte Timer Period Register - Split Mode 21.7.13. High Byte Period Register - Split Mode 21.7.14. Compare Register n For Low Byte Timer - Split Mode 21.7.15. High Byte Compare Register n - Split Mode 22. TCB - 16-bit Timer/Counter Type B 22.1. Features 22.2. Overview 22.2.1. Block Diagram 22.2.2. Signal Description 22.3. Functional Description 22.3.1. Definitions 22.3.2. Initialization 22.3.3. Operation 22.3.3.1. Modes 22.3.3.1.1. Periodic Interrupt Mode 22.3.3.1.2. Time-Out Check Mode 22.3.3.1.3. Input Capture on Event Mode 22.3.3.1.4. Input Capture Frequency Measurement Mode 22.3.3.1.5. Input Capture Pulse-Width Measurement Mode 22.3.3.1.6. Input Capture Frequency and Pulse-Width Measurement Mode 22.3.3.1.7. Single-Shot Mode 22.3.3.1.8. 8-Bit PWM Mode 22.3.3.2. Output 22.3.3.3. 32-Bit Input Capture 22.3.3.4. Noise Canceler 22.3.3.5. Synchronized with Timer/Counter Type A 22.3.4. Events 22.3.5. Interrupts 22.3.6. Sleep Mode Operation 22.4. Register Summary 22.5. Register Description 22.5.1. Control A 22.5.2. Control B 22.5.3. Event Control 22.5.4. Interrupt Control 22.5.5. Interrupt Flags 22.5.6. Status 22.5.7. Debug Control 22.5.8. Temporary Value 22.5.9. Count 22.5.10. Capture/Compare 23. TCD - 12-Bit Timer/Counter Type D 23.1. Features 23.2. Overview 23.2.1. Block Diagram 23.2.2. Signal Description 23.3. Functional Description 23.3.1. Definitions 23.3.2. Initialization 23.3.3. Operation 23.3.3.1. Register Synchronization Categories 23.3.3.2. Waveform Generation Modes 23.3.3.2.1. One Ramp Mode 23.3.3.2.2. Two Ramp Mode 23.3.3.2.3. Four Ramp Mode 23.3.3.2.4. Dual Slope Mode 23.3.3.3. Disabling TCD 23.3.3.4. TCD Inputs 23.3.3.4.1. Input Blanking 23.3.3.4.2. Digital Filter 23.3.3.4.3. Asynchronous Event Detection 23.3.3.4.4. Software Commands 23.3.3.4.5. Input Modes 23.3.3.4.5.1. Input Modes Validity 23.3.3.4.5.2. Input Mode 0: Input Has No Action 23.3.3.4.5.3. Input Mode 1: Stop Output, Jump to Opposite Compare Cycle, and Wait 23.3.3.4.5.4. Input Mode 2: Stop Output, Execute Opposite Compare Cycle, and Wait 23.3.3.4.5.5. Input Mode 3: Stop Output, Execute Opposite Compare Cycle while Fault Active 23.3.3.4.5.6. Input Mode 4: Stop all Outputs, Maintain Frequency 23.3.3.4.5.7. Input Mode 5: Stop all Outputs, Execute Dead Time while Fault Active 23.3.3.4.5.8. Input Mode 6: Stop All Outputs, Jump to Next Compare Cycle, and Wait 23.3.3.4.5.9. Input Mode 7: Stop all Outputs, Wait for Software Action 23.3.3.4.5.10. Input Mode 8: Stop Output on Edge, Jump to Next Compare Cycle 23.3.3.4.5.11. Input Mode 9: Stop Output on Edge, Maintain Frequency 23.3.3.4.5.12. Input Mode 10: Stop Output at Level, Maintain Frequency 23.3.3.4.5.13. Input Mode Summary 23.3.3.5. Dithering 23.3.3.6. TCD Counter Capture 23.3.3.7. Output Control 23.3.4. Events 23.3.4.1. Programmable Output Events 23.3.5. Interrupts 23.3.6. Sleep Mode Operation 23.3.7. Debug Operation 23.3.8. Configuration Change Protection 23.4. Register Summary 23.5. Register Description 23.5.1. Control A 23.5.2. Control B 23.5.3. Control C 23.5.4. Control D 23.5.5. Control E 23.5.6. Event Control A 23.5.7. Event Control B 23.5.8. Interrupt Control 23.5.9. Interrupt Flags 23.5.10. Status 23.5.11. Input Control A 23.5.12. Input Control B 23.5.13. Fault Control 23.5.14. Delay Control 23.5.15. Delay Value 23.5.16. Dither Control 23.5.17. Dither Value 23.5.18. Debug Control 23.5.19. Capture A 23.5.20. Capture B 23.5.21. Compare Set A 23.5.22. Compare Set B 23.5.23. Compare Clear A 23.5.24. Compare Clear B 24. RTC - Real-Time Counter 24.1. Features 24.2. Overview 24.2.1. Block Diagram 24.3. Clocks 24.4. RTC Functional Description 24.4.1. Initialization 24.4.1.1. Configure the Clock CLK_RTC 24.4.1.2. Configure RTC 24.4.2. Operation - RTC 24.4.2.1. Enabling and Disabling 24.5. PIT Functional Description 24.5.1. Initialization 24.5.2. Operation - PIT 24.5.2.1. Enabling and Disabling 24.5.2.2. PIT Interrupt Timing 24.6. Crystal Error Correction 24.7. Events 24.8. Interrupts 24.9. Sleep Mode Operation 24.10. Synchronization 24.11. Debug Operation 24.12. Register Summary 24.13. Register Description 24.13.1. Control A 24.13.2. Status 24.13.3. Interrupt Control 24.13.4. Interrupt Flag 24.13.5. Temporary 24.13.6. Debug Control 24.13.7. Crystal Frequency Calibration 24.13.8. Clock Selection 24.13.9. Count 24.13.10. Period 24.13.11. Compare 24.13.12. Periodic Interrupt Timer Control A 24.13.13. Periodic Interrupt Timer Status 24.13.14. PIT Interrupt Control 24.13.15. PIT Interrupt Flag 24.13.16. Periodic Interrupt Timer Debug Control 25. USART - Universal Synchronous and Asynchronous Receiver and Transmitter 25.1. Features 25.2. Overview 25.2.1. Block Diagram 25.2.2. Signal Description 25.3. Functional Description 25.3.1. Initialization 25.3.2. Operation 25.3.2.1. Frame Formats 25.3.2.2. Clock Generation 25.3.2.2.1. The Fractional Baud Rate Generator 25.3.2.3. Data Transmission 25.3.2.3.1. Disabling the Transmitter 25.3.2.4. Data Reception 25.3.2.4.1. Receiver Error Flags 25.3.2.4.2. Disabling the Receiver 25.3.2.4.3. Flushing the Receive Buffer 25.3.3. Communication Modes 25.3.3.1. Synchronous Operation 25.3.3.1.1. Clock Operation 25.3.3.1.2. External Clock Limitations 25.3.3.1.3. USART in Master SPI Mode 25.3.3.1.3.1. Frame Formats 25.3.3.1.3.2. Clock Generation 25.3.3.1.3.3. Data Transmission 25.3.3.1.3.4. Data Reception 25.3.3.1.3.5. USART in Master SPI Mode vs. SPI 25.3.3.2. Asynchronous Operation 25.3.3.2.1. Clock Recovery 25.3.3.2.2. Data Recovery 25.3.3.2.3. Error Tolerance 25.3.3.2.4. Double-Speed Operation 25.3.3.2.5. Auto-Baud 25.3.3.2.6. Half Duplex Operation 25.3.3.2.6.1. One-Wire Mode 25.3.3.2.6.2. RS-485 Mode 25.3.3.2.7. IRCOM Mode of Operation 25.3.4. Additional Features 25.3.4.1. Parity 25.3.4.2. Start-of-Frame Detection 25.3.4.3. Multiprocessor Communication 25.3.4.3.1. Using Multiprocessor Communication 25.3.5. Events 25.3.6. Interrupts 25.4. Register Summary 25.5. Register Description 25.5.1. Receiver Data Register Low Byte 25.5.2. Receiver Data Register High Byte 25.5.3. Transmit Data Register Low Byte 25.5.4. Transmit Data Register High Byte 25.5.5. USART Status Register 25.5.6. Control A 25.5.7. Control B 25.5.8. Control C - Asynchronous Mode 25.5.9. Control C - Master SPI Mode 25.5.10. Baud Register 25.5.11. Control D 25.5.12. Debug Control Register 25.5.13. IrDA Control Register 25.5.14. IRCOM Transmitter Pulse Length Control Register 25.5.15. IRCOM Receiver Pulse Length Control Register 26. SPI - Serial Peripheral Interface 26.1. Features 26.2. Overview 26.2.1. Block Diagram 26.2.2. Signal Description 26.3. Functional Description 26.3.1. Initialization 26.3.2. Operation 26.3.2.1. Master Mode Operation 26.3.2.1.1. Normal Mode 26.3.2.1.2. Buffer Mode 26.3.2.1.3. SS Pin Functionality in Master Mode - Multi-Master Support 26.3.2.2. Slave Mode 26.3.2.2.1. Normal Mode 26.3.2.2.2. Buffer Mode 26.3.2.2.3. SS Pin Functionality in Slave Mode 26.3.2.3. Data Modes 26.3.2.4. Events 26.3.2.5. Interrupts 26.4. Register Summary 26.5. Register Description 26.5.1. Control A 26.5.2. Control B 26.5.3. Interrupt Control 26.5.4. Interrupt Flags - Normal Mode 26.5.5. Interrupt Flags - Buffer Mode 26.5.6. Data 27. TWI - Two-Wire Interface 27.1. Features 27.2. Overview 27.2.1. Block Diagram 27.2.2. Signal Description 27.3. Functional Description 27.3.1. General TWI Bus Concepts 27.3.2. TWI Basic Operation 27.3.2.1. Initialization 27.3.2.1.1. Master Initialization 27.3.2.1.2. Slave Initialization 27.3.2.2. TWI Master Operation 27.3.2.2.1. Clock Generation 27.3.2.2.2. TWI Bus State Logic 27.3.2.2.3. Transmitting Address Packets 27.3.2.2.3.1. Case M1: Address Packet Transmit Complete - Direction Bit Set to ‘0’ 27.3.2.2.3.2. Case M2: Address Packet Transmit Complete - Direction Bit Set to ‘1’ 27.3.2.2.3.3. Case M3: Address Packet Transmit Complete - Address not Acknowledged by Slave 27.3.2.2.3.4. Case M4: Arbitration Lost or Bus Error 27.3.2.2.4. Transmitting Data Packets 27.3.2.2.5. Receiving Data Packets 27.3.2.3. TWI Slave Operation 27.3.2.3.1. Receiving Address Packets 27.3.2.3.1.1. Case S1: Address Packet Accepted - Direction Bit Set to ‘0’ 27.3.2.3.1.2. Case S2: Address Packet Accepted - Direction Bit Set to ‘1’ 27.3.2.3.1.3. Case S3: Stop Condition Received 27.3.2.3.1.4. Case S4: Collision 27.3.2.3.2. Receiving Data Packets 27.3.2.3.3. Transmitting Data Packets 27.3.3. Additional Features 27.3.3.1. SMBus 27.3.3.2. Multi Master 27.3.3.3. Smart Mode 27.3.3.4. Dual Mode 27.3.3.5. Quick Command Mode 27.3.3.6. 10-bit Address 27.3.4. Interrupts 27.3.5. Sleep Mode Operation 27.3.6. Debug Operation 27.4. Register Summary 27.5. Register Description 27.5.1. Control A 27.5.2. Dual Mode Control Configuration 27.5.3. Debug Control 27.5.4. Master Control A 27.5.5. Master Control B 27.5.6. Master Status 27.5.7. Master Baud Rate 27.5.8. Master Address 27.5.9. Master Data 27.5.10. Slave Control A 27.5.11. Slave Control B 27.5.12. Slave Status 27.5.13. Slave Address 27.5.14. Slave Data 27.5.15. Slave Address Mask 28. CRCSCAN - Cyclic Redundancy Check Memory Scan 28.1. Features 28.2. Overview 28.2.1. Block Diagram 28.3. Functional Description 28.3.1. Initialization 28.3.2. Operation 28.3.2.1. Checksum 28.3.3. Interrupts 28.3.4. Sleep Mode Operation 28.3.5. Debug Operation 28.4. Register Summary 28.5. Register Description 28.5.1. Control A 28.5.2. Control B 28.5.3. Status 29. CCL – Configurable Custom Logic 29.1. Features 29.2. Overview 29.2.1. Block Diagram 29.2.2. Signal Description 29.2.2.1. CCL Input Selection MUX 29.3. Functional Description 29.3.1. Operation 29.3.1.1. Enable-Protected Configuration 29.3.1.2. Enabling, Disabling, and Resetting 29.3.1.3. Truth Table Logic 29.3.1.4. Truth Table Inputs Selection 29.3.1.5. Filter 29.3.1.6. Edge Detector 29.3.1.7. Sequencer Logic 29.3.1.8. Clock Source Settings 29.3.2. Interrupts 29.3.3. Events 29.3.4. Sleep Mode Operation 29.4. Register Summary 29.5. Register Description 29.5.1. Control A 29.5.2. Sequencer Control 0 29.5.3. Sequencer Control 1 29.5.4. Sequencer Control 2 29.5.5. Interrupt Control 0 29.5.6. Interrupt Control 1 29.5.7. Interrupt Flag 29.5.8. LUT n Control A 29.5.9. LUT n Control B 29.5.10. LUT n Control C 29.5.11. TRUTHn 30. AC - Analog Comparator 30.1. Features 30.2. Overview 30.2.1. Block Diagram 30.2.2. Signal Description 30.3. Functional Description 30.3.1. Initialization 30.3.2. Operation 30.3.2.1. Input Hysteresis 30.3.2.2. Input and Reference Selection 30.3.2.3. Normal Mode 30.3.2.4. Power Modes 30.3.2.5. Window Mode 30.3.3. Events 30.3.4. Interrupts 30.3.5. Sleep Mode Operation 30.4. Register Summary 30.5. Register Description 30.5.1. Control A 30.5.2. Control B 30.5.3. MUX Control 30.5.4. DAC Voltage Reference 30.5.5. Interrupt Control 30.5.6. Status 31. ADC - Analog-to-Digital Converter 31.1. Features 31.2. Overview 31.2.1. Block Diagram 31.2.2. Signal Description 31.3. Functional Description 31.3.1. Definitions 31.3.2. Initialization 31.3.3. Operation 31.3.3.1. Operation Modes 31.3.3.2. Starting a Conversion 31.3.3.3. Clock Generation 31.3.3.4. Conversion Timing 31.3.3.4.1. Single Conversion 31.3.3.4.2. Accumulated Conversion 31.3.3.4.3. Free-Running Conversion 31.3.3.4.4. Adjusting Conversion Time 31.3.3.5. Conversion Result (Output Formats) 31.3.3.6. Accumulation 31.3.3.7. Channel Selection 31.3.3.8. Temperature Measurement 31.3.3.9. Window Comparator 31.3.4. I/O Lines and Connections 31.3.5. Events 31.3.6. Interrupts 31.3.7. Debug Operation 31.3.8. Sleep Mode Operation 31.3.9. Synchronization 31.3.10. Configuration Change Protection 31.4. Register Summary 31.5. Register Description 31.5.1. Control A 31.5.2. Control B 31.5.3. Control C 31.5.4. Control D 31.5.5. Control E 31.5.6. Sample Control 31.5.7. MUX Selection for Positive ADC Input 31.5.8. MUX Selection for Negative ADC Input 31.5.9. Command 31.5.10. Event Control 31.5.11. Interrupt Control 31.5.12. Interrupt Flags 31.5.13. Debug Control 31.5.14. Temporary 31.5.15. Result 31.5.16. Window Comparator Low Threshold 31.5.17. Window Comparator High Threshold 32. DAC - Digital-to-Analog Converter 32.1. Features 32.2. Overview 32.2.1. Block Diagram 32.2.2. Signal Description 32.3. Functional Description 32.3.1. Initialization 32.3.2. Operation 32.3.2.1. Enabling, Disabling and Resetting 32.3.2.2. Starting a Conversion 32.3.2.3. DAC as Source For Internal Peripherals 32.3.2.4. DAC Output on Pin 32.3.3. Sleep Mode Operation 32.4. Register Summary 32.5. Register Description 32.5.1. Control A 32.5.2. DATA 33. PTC - Peripheral Touch Controller 33.1. Features 33.2. Overview 33.3. Block Diagram 33.4. Signal Description 33.5. System Dependencies 33.5.1. I/O Lines 33.5.1.1. Mutual Capacitance Sensor Arrangement 33.5.1.2. Self-Capacitance Sensor Arrangement 33.5.2. Clocks 33.6. Functional Description 34. ZCD - Zero-Cross Detector 34.1. Features 34.2. Overview 34.2.1. Block Diagram 34.2.2. Signal Description 34.3. Functional Description 34.3.1. Initialization 34.3.2. Operation 34.3.2.1. External Resistor Selection 34.3.2.2. ZCD Logic Output 34.3.2.3. Correction for ZCPINV Offset 34.3.2.3.1. Correction By Offset Current 34.3.2.3.2. Correction by AC Coupling 34.3.2.4. Handling VPEAK Variations 34.3.3. Events 34.3.4. Interrupts 34.3.5. Sleep Mode Operation 34.4. Register Summary - ZCDn 34.5. Register Description 34.5.1. Control A 34.5.2. Interrupt Control 34.5.3. Status 35. UPDI - Unified Program and Debug Interface 35.1. Features 35.2. Overview 35.2.1. Block Diagram 35.2.2. Clocks 35.2.3. Physical Layer 35.2.4. Pinout Description 35.3. Functional Description 35.3.1. Principle of Operation 35.3.1.1. UPDI UART 35.3.1.2. BREAK Character 35.3.1.2.1. BREAK in One-Wire Mode 35.3.1.3. SYNCH Character 35.3.1.3.1. SYNCH in One-Wire Mode 35.3.2. Operation 35.3.2.1. UPDI Enabling 35.3.2.1.1. One-Wire Enable 35.3.2.2. UPDI Disabling 35.3.2.2.1. Disable During Start-up 35.3.2.2.1.1. Time-Out Disable 35.3.2.2.1.2. Incorrect SYNCH pattern 35.3.2.2.2. UPDI Regular Disable 35.3.2.3. UPDI Communication Error Handling 35.3.2.4. Direction Change 35.3.3. UPDI Instruction Set 35.3.3.1. LDS - Load Data from Data Space Using Direct Addressing 35.3.3.2. STS - Store Data to Data Space Using Direct Addressing 35.3.3.3. LD - Load Data from Data Space Using Indirect Addressing 35.3.3.4. ST - Store Data from UPDI to Data Space Using Indirect Addressing 35.3.3.5. LDCS - Load Data from Control and Status Register Space 35.3.3.6. STCS (Store Data to Control and Status Register Space) 35.3.3.7. REPEAT - Set Instruction Repeat Counter 35.3.3.8. KEY - Set Activation Key or Send System Information Block 35.3.4. CRC Checking of Flash During Boot 35.3.5. Inter-Byte Delay 35.3.6. System Information Block 35.3.7. Enabling of Key Protected Interfaces 35.3.7.1. Chip Erase 35.3.7.2. NVM Programming 35.3.7.3. User Row Programming 35.3.8. Events 35.3.9. Sleep Mode Operation 35.4. Register Summary 35.5. Register Description 35.5.1. Status A 35.5.2. Status B 35.5.3. Control A 35.5.4. Control B 35.5.5. ASI Key Status 35.5.6. ASI Reset Request 35.5.7. ASI Control A 35.5.8. ASI System Control A 35.5.9. ASI System Status 35.5.10. ASI CRC Status 36. Instruction Set Summary 37. Electrical Characteristics 37.1. Disclaimer 37.2. Absolute Maximum Ratings 37.3. Standard Operating Conditions 37.4. DC Characteristics 37.4.1. Supply Voltage 37.4.2. Power Consumption 37.4.3. Peripherals Power Consumption 37.4.4. I/O Pin Characteristics 37.4.5. Memory Programming Specifications 37.4.6. Thermal Characteristics 37.5. AC Characteristics 37.5.1. Internal Oscillator Parameters(1) 37.5.2. Reset, WDT, Oscillator Start-up Timer, Power-up Timer, Brown-out Detector Specifications 37.5.3. Internal Voltage Reference (VREF) Characteristics 37.5.4. USART 37.5.5. SPI 37.5.6. TWI 37.5.7. DAC Specifications 37.5.8. ADC Accuracy Specifications(1) 37.5.9. ADC Conversion Timing Specifications 37.5.10. Analog Comparator Specifications 37.5.11. PTC 37.5.12. Zero-Cross Detector Specifications 37.5.13. UPDI Timing 38. Typical Characteristics 39. Ordering Information 40. Package Drawings 40.1. Online Package Drawings 40.2. 28-Pin SPDIP 40.3. 28-Pin SOIC 40.4. 28-Pin SSOP 40.5. 32-Pin VQFN 40.6. 32-Pin TQFP 40.7. 48-Pin VQFN 40.8. 48-Pin TQFP 40.9. 64-Pin VQFN 40.10. 64-Pin TQFP 41. Data Sheet Revision History 41.1. Rev. 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