Datasheet ES8311 (Everest Semiconductor) - 5

Everest Semiconductor Confidential ES8311 4. CLOCK MODES AND SAMPLING FREQUENCIES
The device supports standard audio clocks (64F, 128Fs, 256Fs, 384Fs, 512Fs, etc), USB clocks (12/24 MHz), and some common non standard audio clocks (16 MHz, 25 MHz, 26 MHz, etc). According to the serial audio data sampling frequency (Fs), the device can work in two speed modes: single speed mode or double speed mode. In single speed mode, Fs normal y ranges from 8 kHz to 48 kHz, and in double speed mode, Fs normal y range from 64 kHz to 96 kHz. The device can work either in master clock mode or slave clock mode. In slave mode, LRCK and SCLK are supplied externally, and LRCK and SCLK must be synchronously derived from the system clock with specific rates. In master mode, LRCK and SCLK are derived internally from device master clock.
5. MICRO-CONTROLLER CONFIGURATION INTERFACE
The device supports standard I2C micro-control er configuration interface. External micro- control er can completely configure the device through writing to internal configuration registers. I2C interface is a bi-directional serial bus that uses a serial data line (CDATA) and a serial clock line (CCLK) for data transfer. The timing diagram for data transfer of this interface is given in Figure 1a and Figure 1b. Data are transmitted synchronously to CCLK clock on the CDATA line on a byte-by-byte basis. Each bit in a byte is sampled during CCLK high with MSB bit being transmitted firstly. Each transferred byte is fol owed by an acknowledge bit from receiver to pul the CDATA low. The transfer rate of this interface can be up to 400 kbps. A master control er initiates the transmission by sending a “start” signal, which is defined as a high-to-low transition at CDATA while CCLK is high. The first byte transferred is the slave address. It is a seven-bit chip address fol owed by a RW bit. The chip address must be 0011 00x, where x equals CE. The RW bit indicates the slave data transfer direction. Once an acknowledge bit is received, the data transfer starts to proceed on a byte-by-byte basis in the direction specified by the RW bit. The master can terminate the communication by generating a “stop” signal, which is defined as a low-to-high transition at CDATA while CCLK is high. In I2C interface mode, the registers can be written and read. The formats of “write” and “read” instructions are shown in Table 1 and Table 2. Please note that, to read data from a register, you must set R/W bit to 0 to access the register address and then set R/W to 1 to read data from the register. Table 1 Write Data to Register in I2C Interface Mode Chip Address R/W Register Address Data to be written start 0011 00 CE 0 ACK RAM ACK DATA ACK Stop Revision 7.0 5 January 2020 Latest datasheet: www.everest-semi.com or info@everest-semi.com Document Outline Block Diagram Pin Out and Description typical APPLICATION CIRCUIT Clock Modes and Sampling Frequencies Micro-controller configuration Interface Digital Audio Interface ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Recommended Operating Conditions ADC Analog and Filter Characteristics and Specifications DAC Analog and Filter Characteristics and Specifications DC Characteristics Serial Audio Port Switching Specifications I2C Switching Specifications (slow speed mode/high speed mode) Package CORPORATe INFORMATION