Datasheet AD8221-KGD (Analog Devices) - 7

Known Good Die AD8221-KGD PIN CONFIGURATION AND FUNCTION DESCRIPTIONS –IN 1 R 2A G 8 +V R S G 2B RG 3A 7 AD8221-KGD VOUT R 3B G 6 REF +IN 4
002
5 –VS
20258- Figure 2. Pad Configuration
Table 3. Pad Function Descriptions Pad No.1 Mnemonic1 Pad Type X Coordinate (µm)2 Y Coordinate (µm)2 Description
1 −IN Single −379 +951 Negative Input Pad 2A RG Double −446 +826 Gain Setting Pad 2B RG Single −615 +474 Gain Setting Pad 3A RG Single −619 +211 Gain Setting Pad 3B RG Double −490 −190 Gain Setting Pad 4 +IN Single −621 −622 Positive Input Pad 5 −VS Single +635 −823 Negative Power Supply Pad 6 REF Double +649 −339 Reference Voltage Pad 7 VOUT Single +612 +84 Output Pad 8 +VS Single +636 +570 Positive Power Supply Pad 1 To minimize gain errors introduced by the bond wires, use Kelvin connections between the chip and the gain resistor, RG, by connecting Pad 2A and Pad 2B in parallel to one end of RG and Pad 3A and Pad 3B in paral el to the other end of RG. For unity-gain applications where RG is not required, Pad 2A and Pad 2B must be bonded together as well as Pad 3A and Pad 3B. 2 The pad coordinates indicate the center of each pad, referenced to the center of the die. Rev. 0 | Page 7 of 8 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION CONNECTION DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS OUTLINE DIMENSIONS DIE SPECIFICATIONS AND ASSEMBLY RECOMMENDATIONS ORDERING GUIDE