Datasheet AD8421-KGD (Analog Devices) - 7
| Hersteller | Analog Devices |
| Beschreibung | 3 nV /√Hz, Low Power Instrumentation Amplifier |
| Seiten / Seite | 8 / 7 — Known Good Die. AD8421-KGD. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. … |
| Dateiformat / Größe | PDF / 248 Kb |
| Dokumentensprache | Englisch |
Known Good Die. AD8421-KGD. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. TOP VIEW. (Not to Scale)
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Known Good Die AD8421-KGD PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 8 AD8421-KGD 1 2A 2B 3A 7B 3B 7A 4 6 5 TOP VIEW
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20316- Figure 2. Pad Configuration
Table 3. Pad Function Descriptions1 Pad No. Mnemonic Pad Type X-Axis (µm) Y-Axis (µm) Description
1 −IN Single −548.2 +376 Negative Input Pad. 2A RG Double −548.2 +241 Gain Setting Pad. 2B RG Double −548.2 +66 Gain Setting Pad. 3A RG Double −548.2 −112 Gain Setting Pad. 3B RG Double −548.2 −287 Gain Setting Pad. 4 +IN Single −548.2 −422 Positive Input Pad. 5 −VS Single +566.4 −841 Negative Power Supply Pad. 6 REF Double +502 −565.8 Reference Voltage Pad. 7A VOUT Single +512 −359.5 Output Pad. 7B VOUT Double +512 −191.6 Output Pad. 8 +VS Single +635.8 +929 Positive Power Supply Pad. 1 To minimize gain errors introduced by the bond wires, use Kelvin connections between the chip and the gain resistor, RG, by connecting Pad 2A and Pad 2B in parallel to one end of RG and by connecting Pad 3A and Pad 3B in paral el to the other end of RG. For unity-gain applications where RG is not required, Pad 2A and Pad 2B must be bonded together as wel as Pad 3A and Pad 3B. Rev. 0 | Page 7 of 8 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS OUTLINE DIMENSIONS DIE SPECIFICATIONS AND ASSEMBLY RECOMMENDATIONS ORDERING GUIDE
002
(Not to Scale)
20316- Figure 2. Pad Configuration
Table 3. Pad Function Descriptions1 Pad No. Mnemonic Pad Type X-Axis (µm) Y-Axis (µm) Description
1 −IN Single −548.2 +376 Negative Input Pad. 2A RG Double −548.2 +241 Gain Setting Pad. 2B RG Double −548.2 +66 Gain Setting Pad. 3A RG Double −548.2 −112 Gain Setting Pad. 3B RG Double −548.2 −287 Gain Setting Pad. 4 +IN Single −548.2 −422 Positive Input Pad. 5 −VS Single +566.4 −841 Negative Power Supply Pad. 6 REF Double +502 −565.8 Reference Voltage Pad. 7A VOUT Single +512 −359.5 Output Pad. 7B VOUT Double +512 −191.6 Output Pad. 8 +VS Single +635.8 +929 Positive Power Supply Pad. 1 To minimize gain errors introduced by the bond wires, use Kelvin connections between the chip and the gain resistor, RG, by connecting Pad 2A and Pad 2B in parallel to one end of RG and by connecting Pad 3A and Pad 3B in paral el to the other end of RG. For unity-gain applications where RG is not required, Pad 2A and Pad 2B must be bonded together as wel as Pad 3A and Pad 3B. Rev. 0 | Page 7 of 8 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS OUTLINE DIMENSIONS DIE SPECIFICATIONS AND ASSEMBLY RECOMMENDATIONS ORDERING GUIDE