Datasheet 8V97003 (IDT) - 8
| Hersteller | IDT |
| Beschreibung | 171.875MHz to 18GHz RF / mmWave Wideband Synthesizer with Integrated VCO |
| Seiten / Seite | 66 / 8 — Pin Assignments Figure 1. Pin Assignments for 7 × 7 mm 48-VFQFPN Package … |
| Revision | 20200120 |
| Dateiformat / Größe | PDF / 1.3 Mb |
| Dokumentensprache | Englisch |
Pin Assignments Figure 1. Pin Assignments for 7 × 7 mm 48-VFQFPN Package ― Top View. 8V97003
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8V97003 Datasheet
Pin Assignments Figure 1. Pin Assignments for 7 × 7 mm 48-VFQFPN Package ― Top View
48 47 46 45 44 43 42 41 40 39 38 37 VREFVCO2 1 36 NC NC 2 35 VREFVCO1 VDDVCO2 3 34 NC VREGVCO2 4 33 VDDVCO1 VTUNE 5 32 VREGVCO1 NC 6 31 nRESET
8V97003
MUTE 7 30 SYNC LD 8 29 CE NC 9 28 SDIO CPOUT 10 27 SDO CPBIAS 11 26 SCLK VDDPDCP 12 25 CSB 13 14 15 16 17 18 19 20 21 22 23 24
Pin Descriptions Table 1. Pin Descriptions Pull-up/ Pin Number Name Type Pull-Down Description
1 VREFVCO2 Analog Reference node for VCO regulator. Connect 22µF capacitor from this pin to GND. 2 NC Unused Do not connect. 3 VDDVCO2 Power VDD power supply for VCO. 4 VREGVCO2 Analog Regulator for VCO. Connect 22µF capacitor from this pin to GND. 5 VTUNE Analog VCO Tuning Voltage. 6 NC Unused Do not connect. 7 MUTE Input PD Outputs disable / High-Impedance. 1.8V LVCMOS logic levels (3.3V tolerant). 8 LD Output Lock Detector (CMOS). 9 NC Unused Do not connect. 10 CPOUT Analog Charge Pump Output. ©2020 Renesas Electronics Corporation 8 January 20, 2020 Document Outline Description Typical Applications Features Simplified Block Diagram Block Diagram Contents List of Figures List of Tables Pin Assignments Pin Descriptions Absolute Maximum Ratings Recommended Operating Conditions Thermal Characteristics and Reliability Information DC Electrical Characteristics AC Electrical Characteristics Typical Performance Characteristics Theory of Operation Synthesizer Programming Reference Input Stage Input Reference Divider (R) Reference Doubler Reference Multiplier (MULT) Feedback Divider Phase and Frequency Detector (PFD) and Charge Pump PFD Frequency External Loop Filter Charge Pump High-Impedance Integrated Low Noise VCO Output Clock Distribution and Optional Output Doubler Output Matching Band Selection Disable Phase Adjust RF Output Power Output Phase Synchronization Power-Down Mode Default Power-Up Conditions VCO Calibration 3- or 4-Wire SPI Interface Description 3/4-Wire Mode Active Clock Edge Reset Least Significant Bit Position Addressing Read Operation Mirrored Register Bits Double-Buffered Registers Operation Protocols Register Map Register Block Descriptions Preface Registers Feedback Divider Control Registers Phase Adjustments Control Registers DSM Control Registers Calibration Control Registers Band Select Clock Divider Control Registers Lock Detect Control Registers Power Down Control Registers Input Control Registers Charge Pump Control Registers Re-Sync Control Registers Output Control Registers Status Registers Applications Information Loop Filter Calculations Recommendations for Unused Input and Output Pins Schematic Example Power Considerations Package Outline Drawings Marking Diagram Ordering Information Revision History
Pin Assignments Figure 1. Pin Assignments for 7 × 7 mm 48-VFQFPN Package ― Top View
48 47 46 45 44 43 42 41 40 39 38 37 VREFVCO2 1 36 NC NC 2 35 VREFVCO1 VDDVCO2 3 34 NC VREGVCO2 4 33 VDDVCO1 VTUNE 5 32 VREGVCO1 NC 6 31 nRESET
8V97003
MUTE 7 30 SYNC LD 8 29 CE NC 9 28 SDIO CPOUT 10 27 SDO CPBIAS 11 26 SCLK VDDPDCP 12 25 CSB 13 14 15 16 17 18 19 20 21 22 23 24
Pin Descriptions Table 1. Pin Descriptions Pull-up/ Pin Number Name Type Pull-Down Description
1 VREFVCO2 Analog Reference node for VCO regulator. Connect 22µF capacitor from this pin to GND. 2 NC Unused Do not connect. 3 VDDVCO2 Power VDD power supply for VCO. 4 VREGVCO2 Analog Regulator for VCO. Connect 22µF capacitor from this pin to GND. 5 VTUNE Analog VCO Tuning Voltage. 6 NC Unused Do not connect. 7 MUTE Input PD Outputs disable / High-Impedance. 1.8V LVCMOS logic levels (3.3V tolerant). 8 LD Output Lock Detector (CMOS). 9 NC Unused Do not connect. 10 CPOUT Analog Charge Pump Output. ©2020 Renesas Electronics Corporation 8 January 20, 2020 Document Outline Description Typical Applications Features Simplified Block Diagram Block Diagram Contents List of Figures List of Tables Pin Assignments Pin Descriptions Absolute Maximum Ratings Recommended Operating Conditions Thermal Characteristics and Reliability Information DC Electrical Characteristics AC Electrical Characteristics Typical Performance Characteristics Theory of Operation Synthesizer Programming Reference Input Stage Input Reference Divider (R) Reference Doubler Reference Multiplier (MULT) Feedback Divider Phase and Frequency Detector (PFD) and Charge Pump PFD Frequency External Loop Filter Charge Pump High-Impedance Integrated Low Noise VCO Output Clock Distribution and Optional Output Doubler Output Matching Band Selection Disable Phase Adjust RF Output Power Output Phase Synchronization Power-Down Mode Default Power-Up Conditions VCO Calibration 3- or 4-Wire SPI Interface Description 3/4-Wire Mode Active Clock Edge Reset Least Significant Bit Position Addressing Read Operation Mirrored Register Bits Double-Buffered Registers Operation Protocols Register Map Register Block Descriptions Preface Registers Feedback Divider Control Registers Phase Adjustments Control Registers DSM Control Registers Calibration Control Registers Band Select Clock Divider Control Registers Lock Detect Control Registers Power Down Control Registers Input Control Registers Charge Pump Control Registers Re-Sync Control Registers Output Control Registers Status Registers Applications Information Loop Filter Calculations Recommendations for Unused Input and Output Pins Schematic Example Power Considerations Package Outline Drawings Marking Diagram Ordering Information Revision History