Datasheet LTC6991 (Analog Devices) - 7

LTC6991
TYPICAL PERFORMANCE CHARACTERISTICS V+ = 3.3V, RSET = 200k, TA = 25°C unless otherwise noted. Output Resistance vs Supply Current Typical Start-Up with POL = 1
50 45 40 35 V+ OUTPUT SOURCING CURRENT 1V/DIV ANCE (Ω) 30 1µs (tMASTER) WIDE INITIAL PULSE 25 20 500µs 15 OUTPUT SINKING CURRENT OUT OUTPUT RESIST 1V/DIV 10 5 0 2 3 4 5 6 V+ = 2.5V 250µs/DIV 6991 G19 SUPPLY VOLTAGE (V) DIVCODE = 15 6991 G22 RSET = 50k
PIN FUNCTIONS (DCB/S6) V+ (Pin 1/Pin 5):
Supply Voltage (2.25V to 5.5V). This and 50ppm/°C or better temperature coefficient. For lower supply should be kept free from noise and ripple. It should accuracy applications an inexpensive 1% thick film resis- be bypassed directly to the GND pin with a 0.1µF capacitor. tor may be used.
DIV (Pin 2/Pin 4):
Programmable Divider and Polarity Limit the capacitance on the SET pin to less than 10pF Input. A V+ referenced A/D converter monitors the DIV to minimize jitter and ensure stability. Capacitance less pin voltage (VDIV) to determine a 4-bit result (DIVCODE). than 100pF maintains the stability of the feedback circuit VDIV may be generated by a resistor divider between V+ regulating the VSET voltage. and GND. Use 1% resistors to ensure an accurate result. The DIV pin and resistors should be shielded from the V+ OUT pin or any other traces that have fast edges. Limit RST OUT the capacitance on the DIV pin to less than 100pF so that LTC6991 V+ VDIV settles quickly. The MSB of DIVCODE (POL) deter- GND V+ mines the polarity of the RST and OUT pins. If POL = 0, C1 0.1µF R1 RST is active-high, and forces OUT low. If POL = 1, RST SET DIV is active-low and forces OUT high. 6991 PF RSET R2
SET (Pin 3/Pin 3):
Frequency-Setting Input. The voltage on the SET pin (VSET) is regulated to 1V above GND. The amount of current sourced from the SET pin (I
RST (Pin 4/Pin 1):
Output Reset. The behavior of the RST SET) pro- grams the master oscillator frequency. The I pin is dependent on the polarity bit (POL). The POL bit is SET current range is 1.25µA to 20µA. The output oscillation will stop configured via the DIVCODE setting. When POL = 0, set- if I ting RST high forces OUT low and setting RST low allows SET drops below approximately 500nA. A resistor con- nected between SET and GND is the most accurate way to the output to oscillate. When POL = 1, RST is active low. set the frequency. For best performance, use a precision In that case, setting RST low forces OUT high and setting metal or thin film resistor of 0.5% or better tolerance RST high allows the output to oscillate. Rev. D For more information www.analog.com 7 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts