Datasheet LTC6991 (Analog Devices) - 18

link to page 18 LTC6991
APPLICATIONS INFORMATION
RST OUT LTC6991 GND V+ V+ C1 0.1µF R1 SET DIV RSET R2 V+ R1 C1 C1 V+ V+ OUT RST OUT DIV GND GND V+ R2 SET RST SET DIV R1 RSET RSET R2 6991 F18
DFN PACKAGE TSOT-23 PACKAGE Figure 16. Supply Bypassing and PCB Layout Supply Bypassing and PCB Layout Guidelines
plane and the C1 connection to the ground plane are The LTC6991 is a 2.2% accurate silicon oscillator when recommended to minimize the inductance. Capacitor used in the appropriate manner. The part is simple to use C1 should be a 0.1µF ceramic capacitor. and by following a few rules, the expected performance 2. Place all passive components on the top side of the is easily achieved. Adequate supply bypassing and proper board. This minimizes trace inductance. PCB layout are important to ensure this. 3. Place RSET as close as possible to the SET pin and Figure 16 shows example PCB layouts for both the TSOT- make a direct, short connection. The SET pin is a cur- 23 and DFN packages using 0603 sized passive compo- rent summing node and currents injected into this pin nents. The layouts assume a two layer board with a ground directly modulate the operating frequency. Having a plane layer beneath and around the LTC6991. These lay- short connection minimizes the exposure to signal outs are a guide and need not be followed exactly. pickup. 1. Connect the bypass capacitor, C1, directly to the V+ and 4. Connect RSET directly to the GND pin. Using a long path GND pins using a low inductance path. The connection or vias to the ground plane will not have a significant from C1 to the V+ pin is easily done directly on the top affect on accuracy, but a direct, short connection is layer. For the DFN package, C1’s connection to GND recommended and easy to apply. is also simply done on the top layer. For the TSOT-23, 5. Use a ground trace to shield the SET pin. This provides OUT can be routed through the C1 pads to allow a good another layer of protection from radiated signals. C1 GND connection. If the PCB design rules do not allow that, C1’s GND connection can be accomplished 6. Place R1 and R2 close to the DIV pin. A direct, short through multiple vias to the ground plane. Multiple connection to the DIV pin minimizes the external signal vias for both the GND pin connection to the ground coupling. Rev. D 18 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts