Datasheet LT3755, LT3755-1, LT3755-2 (Analog Devices) - 9

LT3755/LT3755-1/LT3755-2
PIN FUNCTIONS (MSOP/QFN) PWMOUT (Pin 1/Pin 11):
Buffered Version of PWM Signal an offset for 0V < VCTRL < 1V. For VCTRL > 1.2V the current for Driving LED Load Disconnect NMOS or Level Shift. sense threshold is constant at the full-scale value of 100mV. This pin also serves in a protection function for the FB For 1V < VCTRL < 1.2V, the dependence of current sense overvoltage condition—wil toggle if the FB input is greater threshold upon VCTRL transitions from a linear function than the FB regulation voltage (VFB) plus 60mV (typical). to a constant value, reaching 98% of full-scale value by The PWMOUT pin is driven from INTVCC. Use of a FET with VCTRL = 1.1V. Do not leave this pin open. gate cut-off voltage higher than 1V is recommended.
VREF (Pin 7/Pin 1):
Voltage Reference Output Pin, Typically
FB (Pin 2/Pin 12):
Voltage Loop Feedback Pin. FB is 2V. This pin drives a resistor divider for the CTRL pin, either intended for constant-voltage regulation or for LED protec- for analog dimming or for temperature limit/compensation tion/open LED detection. The internal transconductance of LED load. Can supply up to 100μA. amplifier with output VC will regulate FB to 1.25V (nominal)
PWM (Pin 8/Pin 2):
A signal low turns off switcher, idles through the DC/DC converter. If the FB input is regulating oscillator and disconnects VC pin from all internal loads. the loop, the OPENLED pull-down is asserted. This ac- PWMOUT pin follows PWM pin. PWM has an internal pull- tion may signal an open LED fault. If FB is driven above down resistor. If not used, connect to INTV the FB threshold (by an external power supply spike, for CC. example), the OPENLED pull-down will be de-asserted and
OPENLED (Pin 9/Pin 3, LT3755 and LT3755-2):
An the PWMOUT pin will be driven low to protect the LEDs open-collector pull-down on OPENLED asserts if the FB from an overcurrent event. Do not leave the FB pin open. input is greater than the FB regulation threshold minus If not used, connect to GND. 50mV (typical). To function, the pin requires an external pull-up current less than 1mA. When the PWM input is low
ISN (Pin 3/Pin 13):
Connection Point for the Negative and the DC/DC converter is idle, the OPENLED condition Terminal of the Current Feedback Resistor. If ISN is greater is latched to the last valid state when the PWM input was than 2.9V, the LED current can be programmed by ILED = high. When PWM input goes high again, the OPENLED 100mV/RLED when VCTRL > 1.2V or ILED = (VCTRL –100mV)/ pin will be updated. This pin may be used to report an (10 • RLED) when VCTRL ≤ 1V. Input bias current is typi- open LED fault. cally 25µA. Below 3V, ISN is an input to the short-circuit protection feature that forces GATE to 0V if ISP exceeds
SYNC (Pin 9/Pin 3, LT3755-1 Only):
The SYNC pin is used ISN by more than 150mV (typ). to synchronize the internal oscillator to an external logic level signal. The R
ISP (Pin 4/Pin 14):
Connection Point for the Positive T resistor should be chosen to program an internal switching frequency 20% slower than the SYNC Terminal of the Current Feedback Resistor. Input bias pulse frequency. Gate turn-on occurs a fixed delay after current is dependent upon CTRL pin voltage as shown the rising edge of SYNC. For best PWM performance, the in the TPC. ISP is an input to the short-circuit protection PWM rising edge should occur at least 200ns before the feature when ISN is less than 3V. SYNC rising edge. Use a 50% duty cycle waveform to drive
VC (Pin 5/Pin 15):
Transconductance Error Amplifier this pin. This pin replaces OPENLED on LT3755-1 option Output Pin Used to Stabilize the Voltage Loop with an RC parts. If not used, tie this pin to GND. Network. This pin is high impedance when PWM is low, a
SS (Pin 10/Pin 4):
Soft-Start Pin. This pin modulates feature that stores the demand current state variable for oscillator frequency and compensation pin voltage (VC) the next PWM high transition. Connect a capacitor between clamp. The soft-start interval is set with an external capac- this pin and GND; a resistor in series with the capacitor is itor. The pin has a 10µA (typical) pull-up current source recommended for fast transient response. to an internal 2.5V rail. The soft-start pin is reset to GND
CTRL (Pin 6/Pin 16):
Current Sense Threshold Adjustment by an undervoltage condition (detected by SHDN/UVLO Pin. Regulating threshold V pin) or thermal limit. (ISP – ISN) is 1/10th VCTRL plus Rev. E For more information www.analog.com 9 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts