Datasheet ADT7320 (Analog Devices) - 4

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ADT7320 Data Sheet Parameter Min Typ Max Unit Test Conditions/Comments
Shutdown Current Supply current in shutdown mode At 3.3 V 2.0 15 µA At 5.5 V 5.2 25 µA Power Dissipation, Normal Mode 700 µW VDD = 3.3 V, normal mode at 25°C Power Dissipation, 1 SPS Mode 150 µW Power dissipated for VDD = 3.3 V, TA = 25°C 1 Accuracy specification includes repeatability. 2 The equivalent 3 σ limits are ±0.15°C. This 3 σ specification is provided to enable comparison with other vendors who use these limits. 3 For higher accuracy at 5 V operation, contact Analog Devices, Inc. 4 Temperature hysteresis does not include repeatability. 5 Based on a floating average of 10 readings. 6 Drift includes solder heat resistance and lifetime test performed as per JEDEC Standard JESD22-A108.
SPI TIMING SPECIFICATIONS
TA = −40°C to +150°C, VDD = 2.7 V to 5.5 V, unless otherwise noted. Al input signals are specified with rise time (tR) = fall time (tF) = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
Table 2. Parameter1, 2 Limit at TMIN, TMAX Unit Descriptions
t1 0 ns min CS falling edge to SCLK active edge setup time t2 100 ns min SCLK high pulse width t3 100 ns min SCLK low pulse width t4 30 ns min Data setup time prior to SCLK rising edge t5 25 ns min Data hold time after SCLK rising edge t6 5 ns min Data access time after SCLK falling edge 60 ns max VDD = 4.5 V to 5.5 V 80 ns max VDD = 2.7 V to 3.6 V t 3 7 10 ns min Bus relinquish time after CS inactive edge 80 ns max Bus relinquish time after CS inactive edge t8 0 ns min SCLK inactive edge to CS rising edge hold time t9 0 ns min CS falling edge to DOUT active time 60 ns max VDD = 4.5 V to 5.5 V 80 ns max VDD = 2.7 V to 3.6 V t10 10 ns min SCLK inactive edge to DOUT low 1 Sample tested during initial release to ensure compliance. 2 See Figure 2. 3 This means that the times quoted in the timing characteristics in Table 2 are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.
CS t1 t2 t t 3 8 1 2 3 6 7 8 9 10 23 24 SCLK t4 t5 MSB LSB DIN t6 t t 10 9 DOUT
002
MSB LSB t
09012-
7
Figure 2. Detailed SPI Timing Diagram Rev. 0 | Page 4 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION PRODUCT HIGHLIGHTS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS SPI TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER DETAILS CONTINUOUS CONVERSION MODE ONE-SHOT MODE CT and INT Operation in One-Shot Mode 1 SPS MODE SHUTDOWN MODE FAULT QUEUE TEMPERATURE DATA FORMAT TEMPERATURE CONVERSION FORMULAS 16-Bit Temperature Data Format 13-Bit Temperature Data Format 10-Bit Temperature Data Format 9-Bit Temperature Data Format REGISTERS STATUS REGISTER CONFIGURATION REGISTER TEMPERATURE VALUE REGISTER ID REGISTER TCRIT SETPOINT REGISTER THYST SETPOINT REGISTER THIGH SETPOINT REGISTER TLOW SETPOINT REGISTER SERIAL INTERFACE SPI COMMAND BYTE WRITING DATA READING DATA INTERFACING TO DSPs OR MICROCONTROLLERS SERIAL INTERFACE RESET INT AND CT OUTPUTS UNDERTEMPERATURE AND OVERTEMPERATURE DETECTION Comparator Mode Interrupt Mode APPLICATIONS INFORMATION THERMAL RESPONSE TIME SUPPLY DECOUPLING POWERING FROM A SWITCHING REGULATOR TEMPERATURE MEASUREMENT QUICK GUIDE TO MEASURING TEMPERATURE OUTLINE DIMENSIONS ORDERING GUIDE