Datasheet LTC3307A (Analog Devices) - 9

LTC3307A
PIN FUNCTIONS AGND (Pin 1):
The AGND pin is the output voltage remote
SW (Pins 5, 6):
The SW pins are the switching outputs of ground sense. Connect the AGND pin directly to the nega- the internal power switches. Connect these pins together tive terminal of the output capacitor at the load. The AGND and to the inductor with a short, wide trace. pin is also the ground reference for the internal analog cir-
MODE/SYNC (Pin 9):
The MODE/SYNC pin is a mode cuitry. Place a small analog bypass 0201 or 0402 ceramic selection and external clock synchronization input. Ground capacitor as close as possible to the VIN (Pin 3) and AGND this pin to enable Pulse Skip mode at light loads. For pins. Connect RT and FB returns to AGND as well. higher efficiency at light loads, tie this pin to VIN to enable
EN (Pin 2):
The EN pin has a precision IC enable thresh- the low-ripple Burst Mode operation. For faster transient old with hysteresis. An external resistor divider, from response, lower noise and full frequency operation over VIN or from another supply, can be used to program the a wide load range, float this pin to enable forced continu- threshold below which the LTC3307A will shut down. If ous mode. Drive MODE/SYNC with an external clock to the precision threshold is not required, tie EN directly synchronize the switcher to the applied frequency. While to VIN. When the EN pin is low the LTC3307A enters a synchronizing, the part operates in the forced continuous low current shutdown mode where all internal circuitry mode. The slope compensation is automatically adapted is disabled. Do not float this pin. to the external clock frequency. In the absence of an
V
external clock the switching frequency is determined by
IN (Pins 3, 8):
The VIN pins supply current to internal circuitry and topside power switch. Connect both V the RT pin. IN pins together with short wide traces and bypass to PGND and
RT (Pin 10):
The RT pin sets the switching frequency with AGND with low ESR capacitors located as close as pos- an external resistor to AGND. If this pin is tied to VIN, the sible to the pins. buck will switch at the default oscillator frequency. If the
PGND (Pins 4, 7, Exposed Pad Pin 13):
The PGND pins external clock is driving the MODE/SYNC pin, the RT pin are the return path of the internal bottom side power is ignored. switch. Connect the negative terminal of the input capaci-
PGOOD (Pin 11):
The PGOOD pin is the open drain output tors as close to the PGND pins as possible. For low para- of an internal power good comparator. When the regulated sitic inductance and good thermal performance, connect output voltage falls below the PGOOD threshold or rises Pin 4 and Pin 7 to a large continuous ground plane on above the overvoltage threshold, this pin is pul ed low. the printed circuit board directly under the LTC3307A. When VIN is above VIN UVLO and the part is in shutdown, The PGND exposed pad is the main electrical and thermal this pin is also pulled low. highway and should be connected to large PCB ground
FB (Pin 12):
Program the output voltage and close the plane(s) with many vias. control loop by connecting this pin to the middle node of a resistor divider between the VOUT and AGND. The LTC3307A regulates FB to 500mV (typical). A phase lead capacitor connected between FB and VOUT may be used to optimize transient response. Rev. A For more information www.analog.com 9 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts