Datasheet IR3888 OptiMOS IPOL (Infineon) - 5
| Hersteller | Infineon |
| Beschreibung | 25 A single-voltage synchronous Buck regulator |
| Seiten / Seite | 49 / 5 — IR 888 OptiMOS™ IPOL. 25 A single-voltage synchronous Buck regulator. … |
| Revision | 01_00 |
| Dateiformat / Größe | PDF / 2.7 Mb |
| Dokumentensprache | Englisch |
IR 888 OptiMOS™ IPOL. 25 A single-voltage synchronous Buck regulator. Functional block diagram. AGND. PGood. Vin. VCC/LDO. VREF. POR
Modelllinie für dieses Datenblatt
Textversion des Dokuments
IR 888 OptiMOS™ IPOL 25 A single-voltage synchronous Buck regulator Functional block diagram 2 Functional block diagram AGND PGood Vin VCC/LDO AGND VREF POR UVP OTP *70%
+ -
LDO VCC EN Fault AGND LDrVin OVP BOOT
+
VREF
-
Hysteresis *120% =5% Turn-on Delay VSNS PVIN PGood
Q S
Prebias HDrVin HDrv
+ Q R
Fault VREF
-
Hysteresis *90% =5% POR VCC
+
Hiccup GATE
-
POR 4.0V DRIVE OVP SW LOGIC OTP VCC EN
+
Fault 1.2V
-
LDrVin LDrv PWM PWM COMP SOFT SS SS/Latch + ADAPTIVE START SET - ON-TIME ZC - + PGND GENERATOR Zero Cross PGND DETECTION SW FB OCP VREF Floor
+
RAMP OVP GENERATOR Latch Off
- +
VSENM GENERATOR Hiccup
+ - S Q
UVP
R
TON/ MODE SW 20ms Delay ILIM ILIM Ref Figure 2 Block diagram
Final Datasheet 5 of 49 V2.1 2019-12-11 Document Outline Revision History Trademarks Disclaimer
+ -
LDO VCC EN Fault AGND LDrVin OVP BOOT
+
VREF
-
Hysteresis *120% =5% Turn-on Delay VSNS PVIN PGood
Q S
Prebias HDrVin HDrv
+ Q R
Fault VREF
-
Hysteresis *90% =5% POR VCC
+
Hiccup GATE
-
POR 4.0V DRIVE OVP SW LOGIC OTP VCC EN
+
Fault 1.2V
-
LDrVin LDrv PWM PWM COMP SOFT SS SS/Latch + ADAPTIVE START SET - ON-TIME ZC - + PGND GENERATOR Zero Cross PGND DETECTION SW FB OCP VREF Floor
+
RAMP OVP GENERATOR Latch Off
- +
VSENM GENERATOR Hiccup
+ - S Q
UVP
R
TON/ MODE SW 20ms Delay ILIM ILIM Ref Figure 2 Block diagram
Final Datasheet 5 of 49 V2.1 2019-12-11 Document Outline Revision History Trademarks Disclaimer