Datasheet PI6CB33601 (Diodes) - 9
| Hersteller | Diodes |
| Beschreibung | Very Low Power 6-Output PCIe Clock Buffer With On-Chip Termination |
| Seiten / Seite | 20 / 9 — PI6CB33601. HCSL Output AC Characteristics (jitter). Spec. Symbol. … |
| Dateiformat / Größe | PDF / 1.3 Mb |
| Dokumentensprache | Englisch |
PI6CB33601. HCSL Output AC Characteristics (jitter). Spec. Symbol. Parameters. Condition. Min. Typ. Max. Limit Units. Note:
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PI6CB33601 HCSL Output AC Characteristics (jitter) Spec Symbol Parameters Condition Min. Typ. Max. Limit Units
PCIe Gen 1(6) 25 35 86 ps(p-p) PCIe Gen 2 Low Band, 10kHz < f < 1.5MHz 0.6 0.8 3 ps PCIe Gen 2 High Band, 1.5MHz < f < Nyquist (50MHz) 0.7 1.2 3.1 ps PCIe Gen 3 (PLL BW of 2-4 or 2-5MHz, CDR =10MHz) 0.25 0.4 1 ps tj Integrated phase jitter PLL PHASEPLL mode (RMS)(1,5) PCIe Gen 4 (PLL BW of 2-4 or 2-5MHz, CDR =10MHz) 0.25 0.4 0.5 ps PCIe Gen 5 (PLL BW of 500k to 1.8MHz. CDR =20MHz)(11) 0.07 0.12 0.15 ps 125MHz, 1.5MHz to 20MHz, -20dB/ decade Rollover < 1.5MHz, -40dB/de- 0.15 0.3 ps cade rolloff > 10MHz 133.33MHz 0.15 0.3 ps PCIe Gen 1 0.01 0.05 ps(p-p) PCIe Gen 2 Low Band, 10kHz < f < 1.5MHz 0.01 0.05 ps PCIe Gen 2 High Band, 1.5MHz < f < Nyquist (50MHz) 0.01 0.05 ps PCIe Gen 3 (PLL BW of 2-4 or 2-5MHz, CDR =10MHz) 0.01 0.05 ps tj Additive Integrated phase PCIe Gen 4 (PLL BW of 2-4 or PHASEA jitter (RMS)(1,5,10) 2-5MHz, CDR =10MHz) 0.01 0.05 ps PCIe Gen 5 (PLL BW of 500k to 1.8MHz. CDR =20MHz)(11) 0.01 0.05 ps 125MHz, 1.5MHz to 20MHz, -20dB/ decade Rollover < 1.5MHz, -40dB/de- 0.01 0.05 ps cade rolloff > 10MHz 133.33MHz 0.01 0.05 ps 156.25MHz 12k to 20MHz 0.01 0.05 ps
Note:
1. Guaranteed by design and characterization, not 100% tested in production 2. Measured from differential waveform 3. Slew rate is measured through the Vswing voltage range centered around differential 0V, within +/-150mV window 4. Slew rate matching is measured through +/-75mV window centered around differential zero 5. See http://www.pcisig.com for complete specs 6. Sample size of at least 100k cycles. This can be extrapolated to 108ps pk-pk @ 1M cycles for a BER of 10-12 7. Duty cycle distortion is the difference in duty cycle between the output and input clock when the device is operated in the PLL bypass mode 8. The Min and Max values of each BW setting track each other, low BW max will never occur with high BW min 9. Applies to all differential outputs 10. For additive jitter RMS value is calculated by the following equation = SQRT [(total jitter)*2 - (input jitter)*2] 11. PCIe Gen 5 v0.9 specification PI6CB33601 www.diodes.com January 2020 Document Number DS41290 Rev 5-2 9 Diodes Incorporated
PI6CB33601 HCSL Output AC Characteristics (jitter) Spec Symbol Parameters Condition Min. Typ. Max. Limit Units
PCIe Gen 1(6) 25 35 86 ps(p-p) PCIe Gen 2 Low Band, 10kHz < f < 1.5MHz 0.6 0.8 3 ps PCIe Gen 2 High Band, 1.5MHz < f < Nyquist (50MHz) 0.7 1.2 3.1 ps PCIe Gen 3 (PLL BW of 2-4 or 2-5MHz, CDR =10MHz) 0.25 0.4 1 ps tj Integrated phase jitter PLL PHASEPLL mode (RMS)(1,5) PCIe Gen 4 (PLL BW of 2-4 or 2-5MHz, CDR =10MHz) 0.25 0.4 0.5 ps PCIe Gen 5 (PLL BW of 500k to 1.8MHz. CDR =20MHz)(11) 0.07 0.12 0.15 ps 125MHz, 1.5MHz to 20MHz, -20dB/ decade Rollover < 1.5MHz, -40dB/de- 0.15 0.3 ps cade rolloff > 10MHz 133.33MHz 0.15 0.3 ps PCIe Gen 1 0.01 0.05 ps(p-p) PCIe Gen 2 Low Band, 10kHz < f < 1.5MHz 0.01 0.05 ps PCIe Gen 2 High Band, 1.5MHz < f < Nyquist (50MHz) 0.01 0.05 ps PCIe Gen 3 (PLL BW of 2-4 or 2-5MHz, CDR =10MHz) 0.01 0.05 ps tj Additive Integrated phase PCIe Gen 4 (PLL BW of 2-4 or PHASEA jitter (RMS)(1,5,10) 2-5MHz, CDR =10MHz) 0.01 0.05 ps PCIe Gen 5 (PLL BW of 500k to 1.8MHz. CDR =20MHz)(11) 0.01 0.05 ps 125MHz, 1.5MHz to 20MHz, -20dB/ decade Rollover < 1.5MHz, -40dB/de- 0.01 0.05 ps cade rolloff > 10MHz 133.33MHz 0.01 0.05 ps 156.25MHz 12k to 20MHz 0.01 0.05 ps
Note:
1. Guaranteed by design and characterization, not 100% tested in production 2. Measured from differential waveform 3. Slew rate is measured through the Vswing voltage range centered around differential 0V, within +/-150mV window 4. Slew rate matching is measured through +/-75mV window centered around differential zero 5. See http://www.pcisig.com for complete specs 6. Sample size of at least 100k cycles. This can be extrapolated to 108ps pk-pk @ 1M cycles for a BER of 10-12 7. Duty cycle distortion is the difference in duty cycle between the output and input clock when the device is operated in the PLL bypass mode 8. The Min and Max values of each BW setting track each other, low BW max will never occur with high BW min 9. Applies to all differential outputs 10. For additive jitter RMS value is calculated by the following equation = SQRT [(total jitter)*2 - (input jitter)*2] 11. PCIe Gen 5 v0.9 specification PI6CB33601 www.diodes.com January 2020 Document Number DS41290 Rev 5-2 9 Diodes Incorporated