Datasheet AD1939 (Analog Devices)

4 ADC/8 DAC with PLL, 192 kHz, 24-Bit Codec Data Sheet AD1939 FEATURES GENERAL DESCRIPTION PLL generated or direct master clock
The AD1939 is a high performance, single-chip codec that
Low EMI design
provides four analog-to-digital converters (ADCs) with
112 dB DAC/107 dB ADC dynamic range and SNR
differential input, and eight digital-to-analog converters (DACs)
−94 dB THD + N
with differential output using the Analog Devices, Inc. patented
Single 3.3 V supply
multibit sigma-delta (Σ-Δ) architecture. An SPI port is included,
Tolerance for 5 V logic inputs
allowing a microcontroller to adjust volume and many other
Supports 24-bits and 8 kHz to 192 kHz sample rates
parameters. The AD1939 operates from 3.3 V digital and analog
Differential ADC input
supplies. The AD1939 is available in a 64-lead (differential
Differential DAC output
output) LQFP package.
Log volume control with autoramp function SPI controllable for flexibility
The AD1939 is designed for low EMI. This consideration is
Software-controllable clickless mute
apparent in both the system and circuit design architectures.
Software power-down
By using the on-board PLL to derive the master clock from the
Right-justified, left-justified, I2S, and TDM modes
LR clock or from an external crystal, the AD1939 eliminates
Master and slave modes up to 16-channel input/output
the need for a separate high frequency master clock and can
64-lead LQFP package
also be used with a suppressed bit clock. The DACs and ADCs
Qualified for automotive applications
are designed using the latest Analog Devices continuous time architectures to further minimize EMI. By using 3.3 V supplies,
APPLICATIONS
power consumption is minimized, further reducing emissions.
Automotive audio systems Home Theater Systems Set-top boxes Digital audio effects processors FUNCTIONAL BLOCK DIAGRAM DIGITAL AUDIO INPUT/OUTPUT AD1939 SERIAL DATA PORT DAC DAC ADC SDATA SDATA DAC OUT IN DIGITAL ANALOG ADC CLOCKS FILTER DAC ANALOG DIGITAL AUDIO AND AUDIO FILTER INPUTS ADC VOLUME OUTPUTS DAC TIMING MANAGEMENT CONTROL AND CONTROL ADC DAC (CLOCK AND PLL) DAC DAC SPI PRECISION CONTROL PORT VOLTAGE REFERENCE CONTROL DATA
001
INPUT/OUTPUT
06071- Figure 1.
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Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Test Conditions Analog Performance Specifications Crystal Oscillator Specifications Digital Input/Output Specifications Power Supply Specifications Digital Filters Timing Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Analog-to-Digital Converters (ADCs) Digital-to-Analog Converters (DACs) Clock Signals Reset and Power-Down Serial Control Port Power Supply and Voltage Reference Serial Data Ports—Data Format Time-Division Multiplexed (TDM) Modes Daisy-Chain Mode Control Registers Definitions PLL and Clock Control Registers DAC Control Registers ADC Control Registers Additional Modes Application Circuits Outline Dimensions Ordering Guide Automotive Products