Datasheet ADAU1328 (Analog Devices) - 3
| Hersteller | Analog Devices |
| Beschreibung | 2 ADC/8 DAC with PLL, 192 kHz, 24-Bit Codec |
| Seiten / Seite | 32 / 3 — Data Sheet. ADAU1328. SPECIFICATIONS TEST CONDITIONS. ANALOG PERFORMANCE … |
| Revision | B |
| Dateiformat / Größe | PDF / 431 Kb |
| Dokumentensprache | Englisch |
Data Sheet. ADAU1328. SPECIFICATIONS TEST CONDITIONS. ANALOG PERFORMANCE SPECIFICATIONS. Table 1. Parameter. Conditions. Min. Typ. Max
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Data Sheet ADAU1328 SPECIFICATIONS TEST CONDITIONS
Performance of al channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications. Supply Voltages (AVDD, DVDD) 3.3 V Temperature Range1 As specified in Table 1 Master Clock 12.288 MHz (48 kHz fS, 256 × fS mode) Input Sample Rate 48 kHz Measurement Bandwidth 20 Hz to 20 kHz Word Width 24 bits Load Capacitance (Digital Output) 20 pF Load Current (Digital Output) ±1 mA or 1.5 kΩ to ½ DVDD supply Input Voltage HI 2.0 V Input Voltage LO 0.8 V 1 Functionally guaranteed at −40°C to +85°C case temperature.
ANALOG PERFORMANCE SPECIFICATIONS
Specifications guaranteed at 25°C (ambient).
Table 1. Parameter Conditions Min Typ Max Unit
ANALOG-TO-DIGITAL CONVERTERS ADC Resolution All ADCs 24 Bits Dynamic Range 20 Hz to 20 kHz, −60 dB input No Filter (RMS) 98 102 dB With A-Weighted Filter (RMS) 100 105 dB Total Harmonic Distortion + Noise −1 dBFS −96 −87 dB Gain Error −10 +10 % Interchannel Gain Mismatch −0.25 +0.25 dB Offset Error −10 0 +10 mV Gain Drift 100 ppm/°C Interchannel Isolation −110 dB CMRR 100 mV rms, 1 kHz 55 dB 100 mV rms, 20 kHz 55 dB Input Resistance 14 kΩ Input Capacitance 10 pF Input Common-Mode Bias Voltage 1.5 V DIGITAL-TO-ANALOG CONVERTERS Dynamic Range 20 Hz to 20 kHz, −60 dB input No Filter (RMS) 98 104 dB With A-Weighted Filter (RMS) 100 106 dB With A-Weighted Filter (Avg) 108 dB Total Harmonic Distortion + Noise 0 dBFS Single-Ended Version Two channels running −92 dB Eight channels running −86 −75 dB Full-Scale Output Voltage 0.88 (2.48) V rms (V p-p) Gain Error −10 +10 % Interchannel Gain Mismatch −0.2 +0.2 dB Offset Error −16 −4 16 mV Gain Drift −30 30 ppm/°C Interchannel Isolation 100 dB Rev. B | Page 3 of 32 Document Outline Features Applications General Description Functional Block Diagram Table of Contents Revision History Specifications Test Conditions Analog Performance Specifications Crystal Oscillator Specifications Digital Input/Output Specifications Power Supply Specifications Digital Filters Timing Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Analog-to-Digital Converters (ADCs) Digital-to-Analog Converters (DACs) Clock Signals Reset and Power-Down Serial Control Port Power Supply and Voltage Reference Serial Data Ports—Data Format Time-Division Multiplexed (TDM) Modes Daisy-Chain Mode Control Registers Definitions PLL and Clock Control Registers DAC Control Registers ADC Control Registers Additional Modes Application Circuits Outline Dimensions Ordering Guide
Data Sheet ADAU1328 SPECIFICATIONS TEST CONDITIONS
Performance of al channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications. Supply Voltages (AVDD, DVDD) 3.3 V Temperature Range1 As specified in Table 1 Master Clock 12.288 MHz (48 kHz fS, 256 × fS mode) Input Sample Rate 48 kHz Measurement Bandwidth 20 Hz to 20 kHz Word Width 24 bits Load Capacitance (Digital Output) 20 pF Load Current (Digital Output) ±1 mA or 1.5 kΩ to ½ DVDD supply Input Voltage HI 2.0 V Input Voltage LO 0.8 V 1 Functionally guaranteed at −40°C to +85°C case temperature.
ANALOG PERFORMANCE SPECIFICATIONS
Specifications guaranteed at 25°C (ambient).
Table 1. Parameter Conditions Min Typ Max Unit
ANALOG-TO-DIGITAL CONVERTERS ADC Resolution All ADCs 24 Bits Dynamic Range 20 Hz to 20 kHz, −60 dB input No Filter (RMS) 98 102 dB With A-Weighted Filter (RMS) 100 105 dB Total Harmonic Distortion + Noise −1 dBFS −96 −87 dB Gain Error −10 +10 % Interchannel Gain Mismatch −0.25 +0.25 dB Offset Error −10 0 +10 mV Gain Drift 100 ppm/°C Interchannel Isolation −110 dB CMRR 100 mV rms, 1 kHz 55 dB 100 mV rms, 20 kHz 55 dB Input Resistance 14 kΩ Input Capacitance 10 pF Input Common-Mode Bias Voltage 1.5 V DIGITAL-TO-ANALOG CONVERTERS Dynamic Range 20 Hz to 20 kHz, −60 dB input No Filter (RMS) 98 104 dB With A-Weighted Filter (RMS) 100 106 dB With A-Weighted Filter (Avg) 108 dB Total Harmonic Distortion + Noise 0 dBFS Single-Ended Version Two channels running −92 dB Eight channels running −86 −75 dB Full-Scale Output Voltage 0.88 (2.48) V rms (V p-p) Gain Error −10 +10 % Interchannel Gain Mismatch −0.2 +0.2 dB Offset Error −16 −4 16 mV Gain Drift −30 30 ppm/°C Interchannel Isolation 100 dB Rev. B | Page 3 of 32 Document Outline Features Applications General Description Functional Block Diagram Table of Contents Revision History Specifications Test Conditions Analog Performance Specifications Crystal Oscillator Specifications Digital Input/Output Specifications Power Supply Specifications Digital Filters Timing Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Analog-to-Digital Converters (ADCs) Digital-to-Analog Converters (DACs) Clock Signals Reset and Power-Down Serial Control Port Power Supply and Voltage Reference Serial Data Ports—Data Format Time-Division Multiplexed (TDM) Modes Daisy-Chain Mode Control Registers Definitions PLL and Clock Control Registers DAC Control Registers ADC Control Registers Additional Modes Application Circuits Outline Dimensions Ordering Guide