Datasheet SSM2603 (Analog Devices) - 8

SSM2603 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS IN IN K E E E N B IN CL DI UT LIN IC S S CS M LLIN R M 28 27 26 25 24 23 22 MCLK/XTI 1 21 MICBIAS XTO 2 20 VMID DCVDD 3 19 AGND SSM2603 DGND 4 18 AVDD TOP VIEW DBVDD 5 (Not to Scale) 17 ROUT CLKOUT 6 16 LOUT BCLK 7 15 PGND 8 9 10 11 12 13 14 RC RC DD UT UT V O O BDAT BL CDAT CL P P HP HP RE RE L RHP NOTES
002
1. CONNECT THE EXPOSED PAD TO THE PCB GROUND LAYER.
07241- Figure 6. Pin Configuration
Table 9. Pin Function Descriptions Pin No. Mnemonic Type Description
1 MCLK/XTI Digital Input Master Clock Input/Crystal Input. 2 XTO Digital Output Crystal Output. 3 DCVDD Digital Supply Digital Core Supply. 4 DGND Digital Ground Digital Ground. 5 DBVDD Digital Supply Digital I/O Supply. 6 CLKOUT Digital Output Buffered Clock Output. 7 BCLK Digital Input/Output Digital Audio Bit Clock. 8 PBDAT Digital Input DAC Digital Audio Data Input, Playback Function. 9 PBLRC Digital Input/Output DAC Sampling Rate Clock, Playback Function (from Left and Right Channels). 10 RECDAT Digital Output ADC Digital Audio Data Output, Record Function. 11 RECLRC Digital Input/Output ADC Sampling Rate Clock, Record Function (from Left and Right Channels). 12 HPVDD Analog Supply Headphone Supply. 13 LHPOUT Analog Output Headphone Output for Left Channel. 14 RHPOUT Analog Output Headphone Output for Right Channel. 15 PGND Analog Ground Headphone Ground. 16 LOUT Analog Output Line Output for Left Channel. 17 ROUT Analog Output Line Output for Right Channel. 18 AVDD Analog Supply Analog Supply. 19 AGND Analog Ground Analog Ground. 20 VMID Analog Output Midrail Voltage Decoupling Input. 21 MICBIAS Analog Output Microphone Bias. 22 MICIN Analog Input Microphone Input Signal. 23 RLINEIN Analog Input Line Input for Right Channel. 24 LLINEIN Analog Input Line Input for Left Channel. 25 MUTE Digital Input DAC Output Mute, Active Low 26 CSB Digital Input 2-Wire Control Interface I2C Address Selection. 27 SDIN Digital Input/Output 2-Wire Control Interface Data Input/Output. 28 SCLK Digital Input 2-Wire Control Interface Clock Input. Exposed Pad Thermal Exposed Pad Connect the exposed pad to the PCB ground layer. Rev. D | Page 8 of 31 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Digital Filter Characteristics Timing Characteristics Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Converter Filter Response Digital De-Emphasis Theory of Operation Digital Core Clock ADC and DAC ADC High-Pass and DAC De-Emphasis Filters Hardware Mute Pin Automatic Level Control (ALC) Decay (Gain Ramp-Up) Time Attack (Gain Ramp-Down) Time Noise Gate Analog Interface Signal Chain Stereo Line and Monaural Microphone Inputs Bypass and Sidetone Paths to Output Line and Headphone Outputs Digital Audio Interface Recording Mode Playback Mode Digital Audio Data Sampling Rate Software Control Interface Control Register Sequencing Typical Application Circuits Register Map Register Map Details Left-Channel ADC Input Volume, Address 0x00 Right-Channel ADC Input Volume, Address 0x01 Left-Channel DAC Volume, Address 0x02 Right-Channel DAC Volume, Address 0x03 Analog Audio Path, Address 0x04 Digital Audio Path, Address 0x05 Power Management, Address 0x06 Power Consumption Digital Audio I/F, Address 0x07 Sampling Rate, Address 0x08 Active, Address 0x09 Software Reset, Address 0x0F ALC Control 1, Address 0x10 ALC Control 2, Address 0x11 Noise Gate, Address 0x12 Outline Dimensions Ordering Guide