Datasheet SSM2603 (Analog Devices) - 6

SSM2603 Data Sheet Table 5. Digital Audio Interface Master Mode Timing Limit Parameter tMIN tMAX Unit Description
tDST 30 ns PBDAT setup time to BCLK rising edge tDHT 10 ns PBDAT hold time to BCLK rising edge tDL 10 ns RECLRC/PBLRC propagation delay from BCLK falling edge tDDA 10 ns RECDAT propagation delay from BCLK falling edge tBCLKR 10 ns BCLK rising time (10 pF load) tBCLKF 10 ns BCLK falling time (10 pF load) tBCLKDS 45:55:00 55:45:00 BCLK duty cycle (normal and USB mode)
BCLK tDL PBLRC/ RECLRC tDST tDHT PBDAT t
026
DDA RECDAT
07241- Figure 4. Digital Audio Interface Master Mode Timing
Table 6. Master Clock Timing1 Limit Parameter tMIN tMAX Unit Description
tXTIY 54 ns MCLK/XTI clock cycle time tMCLKDS 40:60 60:40 MCLK/XTI duty cycle tXTIH 18 ns MCLK/XTI clock pulse width high tXTIL 18 ns MCLK/XTI clock pulse width low tCOP 20 ns CLKOUT propagation delay from MCLK/XTI falling edge tCOPDIV2 20 ns CLKODIV2 propagation delay from MCLK/XTI falling edge 1 CLKDIV2 bit (Register R8, Bit D6) is set to 0.
tXTIH tCOP MCLK/XTI tXTIL tXTIY CLKOUT
5
CLKODIV2
3 0 1-
t
724
COPDIV2
0 Figure 5. System (MCLK) Clock Timing Rev. D | Page 6 of 31 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Digital Filter Characteristics Timing Characteristics Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Converter Filter Response Digital De-Emphasis Theory of Operation Digital Core Clock ADC and DAC ADC High-Pass and DAC De-Emphasis Filters Hardware Mute Pin Automatic Level Control (ALC) Decay (Gain Ramp-Up) Time Attack (Gain Ramp-Down) Time Noise Gate Analog Interface Signal Chain Stereo Line and Monaural Microphone Inputs Bypass and Sidetone Paths to Output Line and Headphone Outputs Digital Audio Interface Recording Mode Playback Mode Digital Audio Data Sampling Rate Software Control Interface Control Register Sequencing Typical Application Circuits Register Map Register Map Details Left-Channel ADC Input Volume, Address 0x00 Right-Channel ADC Input Volume, Address 0x01 Left-Channel DAC Volume, Address 0x02 Right-Channel DAC Volume, Address 0x03 Analog Audio Path, Address 0x04 Digital Audio Path, Address 0x05 Power Management, Address 0x06 Power Consumption Digital Audio I/F, Address 0x07 Sampling Rate, Address 0x08 Active, Address 0x09 Software Reset, Address 0x0F ALC Control 1, Address 0x10 ALC Control 2, Address 0x11 Noise Gate, Address 0x12 Outline Dimensions Ordering Guide