Datasheet ADAU1772 (Analog Devices) - 6

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ADAU1772 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit
Interchannel Gain Mismatch Line output mode 20 mdB Total Harmonic Distortion + Noise Line output mode, 20 Hz to 20 kHz, −1 dBFS dB AVDD = 1.8 V −93 dB AVDD = 3.3 V −94 dB Gain Error Line output mode ±0.1 dB Dynamic Range1 Headphone mode, 20 Hz to 20 kHz, −60 dB input With A-Weighted Filter (RMS) AVDD = 1.8 V 100 dB AVDD = 3.3 V 104 dB With Flat 20 Hz to 20 kHz Filter AVDD = 1.8 V 97 dB AVDD = 3.3 V 101 dB Signal-to-Noise Ratio2 Headphone mode, 20 Hz to 20 kHz With A-Weighted Filter (RMS) AVDD = 1.8 V 100 dB AVDD = 3.3 V 104 dB With Flat 20 Hz to 20 kHz Filter AVDD = 1.8 V 98 dB AVDD = 3.3 V 102 dB Interchannel Gain Mismatch Headphone mode 50 mdB Total Harmonic Distortion + Noise Headphone mode, 20 Hz to 20 kHz, −1 dBFS 32 Ω load AVDD = 1.8 V, PO = 6.7 mW −77 dB AVDD = 3.3 V, PO = 22.4 mW −80 dB 24 Ω load AVDD = 1.8 V, PO = 8.9 mW −76 dB AVDD = 3.3 V, PO = 30 mW −79 dB 16 Ω load AVDD = 1.8 V, PO = 13 mW −74 dB AVDD = 3.3 V, PO = 44 mW −77 dB Headphone Output Power 32 Ω Load AVDD = 1.8 V, <0.1% THD + N 8.4 mW AVDD = 3.3 V, <0.1% THD + N 28.1 mW 24 Ω Load AVDD = 1.8 V, <0.1% THD + N 11.2 mW AVDD = 3.3 V, <0.1% THD + N 37.4 mW 16 Ω Load AVDD = 1.8 V, <0.1% THD + N 16.25 mW AVDD = 3.3 V, <0.1% THD + N 55.8 mW Gain Error Headphone mode ±0.1 dB Offset Error ±0.1 mV Interchannel Isolation 1 kHz, 0 dBFS input signal 100 dB Power Supply Rejection Ratio CM capacitor = 22 μF, 100 mV p-p at 1 kHz 70 dB DAC DIFFERENTIAL OUTPUT Differential operation Full-Scale Output Voltage Scales linearly with AVDD AVDD/1.8 V rms AVDD = 1.8 V 1.0 V rms AVDD = 1.8 V, 0 dBFS 2.58 V p-p AVDD = 3.3 V 1.83 V rms AVDD = 3.3 V, 0 dBFS 5.49 V p-p Mute Attenuation −72 dB Dynamic Range1 Line output mode, 20 Hz to 20 kHz, −60 dB input With A-Weighted Filter (RMS) AVDD = 1.8 V 104 dB AVDD = 3.3 V 107 dB With Flat 20 Hz to 20 kHz Filter AVDD = 1.8 V 101 dB AVDD = 3.3 V 105 dB Signal-to-Noise Ratio2 Line output mode, 20 Hz to 20 kHz With A-Weighted Filter (RMS) AVDD = 1.8 V 105 dB AVDD = 3.3 V 108 dB With Flat 20 Hz to 20 kHz Filter AVDD = 1.8 V 102 dB AVDD = 3.3 V 105 dB Interchannel Gain Mismatch Line output mode 20 mdB Total Harmonic Distortion + Noise Line output mode, 20 Hz to 20 kHz, −1 dBFS dB AVDD = 1.8 V −96 dB AVDD = 3.3 V −96 dB Gain Error Line output mode % Rev. C | Page 6 of 116 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Analog Performance Specifications Crystal Amplifier Specifications Digital Input/Output Specifications Power Supply Specifications Typical Power Consumption Digital Filters Digital Timing Specifications Digital Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics System Block Diagrams Theory of Operation System Clocking and Power-Up Clock Initialization PLL Bypass Setup PLL Enabled Setup Control Port Access During Initialization PLL Input Clock Divider Integer Mode Fractional Mode Clock Output Power Sequencing Power-Down Considerations Signal Routing Input Signal Paths Analog Inputs Signal Polarity Input Impedance Analog Microphone Inputs Analog Line Inputs Precharging Input Capacitors Microphone Bias Digital Microphone Input Analog-to-Digital Converters ADC Full-Scale Level Digital ADC Volume Control High-Pass Filter Output Signal Paths Analog Outputs Headphone Output Headphone Output Power-Up Sequencing Ground-Centered Headphone Configuration Pop-and-Click Suppression Line Outputs Digital-to-Analog Converters DAC Full-Scale Level Digital DAC Volume Control PDM Output Asynchronous Sample Rate Converters Signal Levels Signal Processing Instructions Data Memory Parameters Control Port Burst Mode Communication I2C Port Addressing I2C Read and Write Operations SPI Port Read/Write Subaddress Data Bytes Self-Boot EEPROM Size CRC Delay Boot Time Multipurpose Pins Push-Button Volume Controls Limiter Compression Enable Parameter Bank Switching Mute DSP Bypass Mode Serial Data Input/Output Ports Tristating Unused Channels Applications Information Power Supply Bypass Capacitors Layout Grounding Exposed Pad PCB Design Register Summary Register Details Clock Control Register PLL Denominator MSB Register PLL Denominator LSB Register PLL Numerator MSB Register PLL Numerator LSB Register PLL Integer Setting Register PLL Lock Flag Register CLKOUT Setting Selection Register Regulator Control Register Core Control Register Filter Engine and Limiter Control Register DB Value Register 0 Read DB Value Register 1 Read DB Value Register 2 Read Core Channel 0/Core Channel 1 Input Select Register Core Channel 2/Core Channel 3 Input Select Register DAC Input Select Register PDM Modulator Input Select Register Serial Data Output 0/Serial Data Output 1 Input Select Register Serial Data Output 2/Serial Data Output 3 Input Select Register Serial Data Output 4/Serial Data Output 5 Input Select Register Serial Data Output 6/Serial Data Output 7 Input Select Register ADC_SDATA0/ADC_SDATA1 Channel Select Register Output ASRC0/Output ASRC1 Source Register Output ASRC2/Output ASRC3 Source Register Input ASRC Channel Select Register ADC0/ADC1 Control 0 Register ADC2/ADC3 Control 0 Register ADC0/ADC1 Control 1 Register ADC2/ADC3 Control 1 Register ADC0 Volume Control Register ADC1 Volume Control Register ADC2 Volume Control Register ADC3 Volume Control Register PGA Control 0 Register PGA Control 1 Register PGA Control 2 Register PGA Control 3 Register PGA Slew Control Register PGA 10 dB Gain Boost Register Input and Output Capacitor Charging Register DSP Bypass Path Register DSP Bypass Gain for PGA0 Register DSP Bypass Gain for PGA1 Register MIC_BIAS0_1 Control Register DAC Control Register DAC0 Volume Control Register DAC1 Volume Control Register Headphone Output Mutes Register Serial Port Control 0 Register Serial Port Control 1 Register TDM Output Channel Disable Register PDM Enable Register PDM Pattern Setting Register MP0 Function Setting Register MP1 Function Setting Register MP2 Function Setting Register MP3 Function Setting Register MP4 Function Setting Register MP5 Function Setting Register MP6 Function Setting Register Push-Button Volume Settings Register Push-Button Volume Control Assignment Register Debounce Modes Register Headphone Line Output Select Register Decimator Power Control Register ASRC Interpolator and DAC Modulator Power Control Register Analog Bias Control 0 Register Analog Bias Control 1 Register Digital Pin Pull-Up Control 0 Register Digital Pin Pull-Up Control 1 Register Digital Pin Pull-Down Control 0 Register Digital Pin Pull-Down Control 1 Register Digital Pin Drive Strength Control 0 Register Digital Pin Drive Strength Control 1 Register Outline Dimensions Ordering Guide