Datasheet ADAU1372 (Analog Devices)

Quad ADC, Dual DAC, Low Latency, Low Power Codec Data Sheet ADAU1372 FEATURES APPLICATIONS Low latency, 24-bit ADCs and DACs Handsets, headsets, and headphones 102 dB SNR (through PGA and ADC with A-weighted filter) Bluetooth® handsets, headsets, and headphones 107 dB dynamic range (through DAC and headphone with Personal navigation devices A-weighted filter) Digital still and video cameras Serial port sample rates from 8 kHz to 192 kHz GENERAL DESCRIPTION 4 single-ended analog inputs, configurable as microphone or line inputs
The ADAU1372 is a codec with four inputs and two outputs, which
Dual stereo digital microphone inputs
incorporates asynchronous sample rate converters. Optimized
Stereo analog audio output, single-ended or differential,
for low latency and low power, the ADAU1372 is ideal for headsets,
configurable as either line output or headphone driver
handsets, and headphones. The ADAU1372 has built-in program-
PLL supporting any input clock rate from 8 MHz to 27 MHz
mable gain amplifiers (PGAs); thus, with the addition of just a
Full-duplex, asynchronous sample rate converters (ASRCs)
few passive components and a crystal, the ADAU1372 provides
Power supplies
a solution for headset audio needs, microphone preamplifiers,
Analog and digital input/output of 1.8 V to 3.3 V
ADCs, DACs, headphone amplifiers, and serial ports for
Low power (15.5 mW)
connections to an external DSP.
I2C and SPI control interfaces for flexibility
Note that throughout this data sheet, multifunction pins, such as
5 multipurpose pins supporting dual stereo digital
SCL/SCLK, are referred to either by the entire pin name or by a
microphone inputs, mute, push-button volume controls
single function of the pin, for example, SCLK, when only that function is relevant.
FUNCTIONAL BLOCK DIAGRAM UT _O D DD G DD DD DD D PD DV RE AV AV AV IOV MICBIAS0 MICROPHONE BIAS GENERATORS POWER LDO MICBIAS1 ADAU1372 MANAGEMENT REGULATOR ADC_SDATA1/CLKOUT/MP6 CLOCK PLL XTALI/MCLKIN AIN0REF OSCILLATOR PGA XTALO AIN0 Σ-Δ ADC DECIMATOR AIN1REF HPOUTLP/LOUTLP PGA Σ-Δ AIN1 Σ-Δ ADC DACs HPOUTLN/LOUTLN DECIMATOR INPUT/OUTPUT SIGNAL ROUTING DMIC0_1/MP4 DIGITAL MICROPHONE DMIC2_3/MP5 INPUTS HPOUTRP/LOUTRP Σ-Δ DACs AIN2REF HPOUTRN/LOUTRN PGA DECIMATOR AIN2 Σ-Δ ADC BIDIRECTIONAL ASRCS AIN3REF PGA DECIMATOR SERIAL I/O PORT AIN3 I2C/SPI CONTROL Σ-Δ ADC INTERFACE CM K 0 K 1 S I ND ND ND ND ND P P S S O LK SO M C M DG DG AG AG AG M BCL RCL /MI A/ L A0/ L/S A C DAT ADDR0/ S SD DAT ADDR1/
001
DAC_S
12702-
ADC_S
Figure 1.
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Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ANALOG PERFORMANCE SPECIFICATIONS CRYSTAL AMPLIFIER SPECIFICATIONS DIGITAL INPUT/OUTPUT SPECIFICATIONS POWER SUPPLY SPECIFICATIONS TYPICAL POWER CONSUMPTION DIGITAL FILTERS DIGITAL TIMING SPECIFICATIONS Digital Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION SYSTEM CLOCKING AND POWER-UP INITIALIZATION CLOCK INITIALIZATION PLL Bypass Setup PLL Enabled Setup Control Port Access During Initialization PLL Input Clock Divider Integer Mode Fractional Mode CLOCK OUTPUT POWER SEQUENCING Power-Down Considerations SIGNAL ROUTING INPUT SIGNAL PATHS ANALOG INPUTS Signal Polarity Input Impedance Analog Microphone Inputs Analog Line Inputs Precharging Input Capacitors Microphone Bias DIGITAL MICROPHONE INPUT ANALOG-TO-DIGITAL CONVERTERS ADC Full-Scale Level Digital ADC Volume Control High-Pass Filter OUTPUT SIGNAL PATHS ANALOG OUTPUTS Headphone Output Headphone Output Power-Up Sequencing Ground Centered Headphone Configuration Pop and Click Suppression Line Outputs DIGITAL-TO-ANALOG CONVERTERS DAC Full-Scale Level Digital DAC Volume Control ASYNCHRONOUS SAMPLE RATE CONVERTERS CONTROL PORT BURST MODE COMMUNICATION I2C PORT Addressing I2C Read and Write Operations SPI PORT Read/Write Subaddress Data Bytes BURST MODE COMMUNICATION MULTIPURPOSE PINS PUSH-BUTTON VOLUME CONTROLS MUTE TALKTHROUGH MODE SERIAL DATA INPUT/OUTPUT PORTS SERIAL PORT INITIALIZATION TRISTATING UNUSED CHANNELS APPLICATIONS INFORMATION POWER SUPPLY BYPASS CAPACITORS LAYOUT GROUNDING EXPOSED PAD PCB DESIGN SYSTEM BLOCK DIAGRAM REGISTER SUMMARY: LOW LATENCY CODEC CLOCK CONTROL REGISTER PLL DENOMINATOR MSB REGISTER PLL DENOMINATOR LSB REGISTER PLL NUMERATOR MSB REGISTER PLL NUMERATOR LSB REGISTER PLL INTEGER SETTING REGISTER PLL LOCK FLAG REGISTER CLKOUT SETTING SELECTION REGISTER REGULATOR CONTROL REGISTER DAC INPUT SELECT REGISTER SERIAL DATA OUTPUT 0/SERIAL DATA OUTPUT 1 INPUT SELECT REGISTER SERIAL DATA OUTPUT 2/SERIAL DATA OUTPUT 3 INPUT SELECT REGISTER SERIAL DATA OUTPUT 4/SERIAL DATA OUTPUT 5 INPUT SELECT REGISTER SERIAL DATA OUTPUT 6/SERIAL DATA OUTPUT 7 INPUT SELECT REGISTER ADC_SDATA0/ADC_SDATA1 CHANNEL SELECT REGISTER OUTPUT ASRC0/OUTPUT ASRC1 SOURCE REGISTER OUTPUT ASRC2/OUTPUT ASRC3 SOURCE REGISTER INPUT ASRC CHANNEL SELECT REGISTER ADC CONTROL 0 REGISTER ADC CONTROL 1 REGISTER ADC CONTROL 2 REGISTER ADC CONTROL 3 REGISTER ADC0 VOLUME CONTROL REGISTER ADC1 VOLUME CONTROL REGISTER ADC2 VOLUME CONTROL REGISTER ADC3 VOLUME CONTROL REGISTER PGA CONTROL 0 REGISTER PGA CONTROL 1 REGISTER PGA CONTROL 2 REGISTER PGA CONTROL 3 REGISTER PGA SLEW CONTROL REGISTER PGA 10 dB GAIN BOOST REGISTER INPUT AND OUTPUT CAPACITOR CHARGING REGISTER ADC TO DAC TALKTHROUGH BYPASS PATH REGISTER TALKTHROUGH BYPASS GAIN FOR ADC0 REGISTER TALKTHROUGH BYPASS GAIN FOR ADC1 REGISTER MICBIAS CONTROL REGISTER DAC CONTROL 1 REGISTER DAC0 VOLUME CONTROL REGISTER DAC1 VOLUME CONTROL REGISTER HEADPHONE OUTPUT MUTES REGISTER SERIAL PORT CONTROL 0 REGISTER SERIAL PORT CONTROL 1 REGISTER TDM OUTPUT CHANNEL DISABLE REGISTER MP0 FUNCTION SETTING REGISTER MP1 FUNCTION SETTING REGISTER MP4 FUNCTION SETTING REGISTER MP5 FUNCTION SETTING REGISTER MP6 FUNCTION SETTING REGISTER PUSH-BUTTON VOLUME SETTINGS REGISTER PUSH-BUTTON VOLUME CONTROL ASSIGNMENT REGISTER DEBOUNCE MODES REGISTER HEADPHONE LINE OUTPUT SELECT REGISTER DECIMATOR POWER CONTROL REGISTER ASRC INTERPOLATOR AND DAC MODULATOR POWER CONTROL REGISTER ANALOG BIAS CONTROL 0 REGISTER ANALOG BIAS CONTROL 1 REGISTER DIGITAL PIN PULL-UP CONTROL 0 REGISTER DIGITAL PIN PULL-UP CONTROL 1 REGISTER DIGITAL PIN PULL-DOWN CONTROL 2 REGISTER DIGITAL PIN PULL-DOWN CONTROL 3 REGISTER DIGITAL PIN DRIVE STRENGTH CONTROL 4 REGISTER DIGITAL PIN DRIVE STRENGTH CONTROL 5 REGISTER OUTLINE DIMENSIONS ORDERING GUIDE