Datasheet LTC3897 (Analog Devices) - 6

HerstellerAnalog Devices
BeschreibungPolyPhase Synchronous Boost Controller with Input/Output Protection
Seiten / Seite50 / 6 — ELECTRICAL CHARACTERISTICS. The. denotes the specifications which apply …
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ELECTRICAL CHARACTERISTICS. The. denotes the specifications which apply over the specified operating

ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the specified operating

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ELECTRICAL CHARACTERISTICS The
l
denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V, VBIAS = 12V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
ITMR,UP TMR Pin Pull-Up Current, Overvoltage TMR = 1V, SPFB = 1.5V, VIN – VIS– = 0.5V l –1.5 –2.5 –3.7 µA TMR = 1V, SPFB = 1.5V, VIN – VIS– = 70V l –43 –53 –63 µA TMR Pin Pull-Up Current, Overcurrent TMR = 1V, ΔVIS = 60mV, VIN – VIS– = 0.5V l –6 –10 –16 µA TMR = 1V, ΔVIS = 60mV, VIN – VIS– = 70V l –210 –250 –290 µA TMR Pin Pull-Up Current, Warning TMR = 1.3V, SPFB = 1.5V, VIN – VIS– = 0.5V l –3 –5 –8 µA TMR Pin Pull-Up Current, Retry TMR = 1V, SPFB = 1.5V l –1.5 –2.5 –3.7 µA ITMR,DN TMR Pin Pull-Down Current TMR = 1V, SPFB = 1.5V, Retry l 1.2 2 2.8 µA SGEN = 0V l 0.4 0.75 1.5 mA Retry Duty Cycle, Overcurrent ΔVIS = 60mV, VIN – VIS– = 12V l 0.06 0.08 0.12 % TMR Pin Thresholds SG Falling, VIN = 4.2V to 70V l 1.31 1.35 1.38 V SG Rising (after 32 cycles), VIN = 4.2V to 70V l 0.13 0.15 0.18 V
Ideal Diode
DGEN Pin ON Threshold VDGEN Rising l 1.16 1.26 1.36 V DGEN Pin Hysteresis 100 mV DG Pin Output High Voltage, (VDG − VCS) VIN = 4.2V, IDG = 0, −1µA, No Fault, SG Open l 4.5 V 8V < VIN < 70V, IDG = 0, −1µA, No Fault, SG l 10 12 16 V Open DG Pin Pull-Up Current DG = CS = VIN = 12V, CS – IS+ = 0.1V l –5 –10 –15 µA DG Pin Pull-Down Current DG = CS + 5V, CS – IS+ = –0.2V l 60 130 mA DG = CS + 5V, SGEN = DGEN = 0V l 0.4 1 mA ΔVSD Source-Drain Regulation Voltage, (VCS DG – CS = 2.5V, VIN = CS = 4.2V to 70V l 20 30 40 mV − VIS+) DG Turn Off Propagation Delay in Fault CS – IS+ = –1V, DG High to Low l 0.6 2 µS Condition
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 3:
This IC includes overtemperature protection that is intended to may cause permanent damage to the device. Exposure to any Absolute protect the device during momentary overload conditions. The maximum Maximum Rating condition for extended periods may affect device rated junction temperature will be exceeded when this protection is active. reliability and lifetime. Continuous operation above the specified absolute maximum operating
Note 2:
The LTC3897 is tested under pulsed load conditions such junction temperature may impair device reliability or permanently damage that T the device. J ≈ TA. The LTC3897E is guaranteed to meet specifications from 0°C to 85°C junction temperature. Specifications over the –40°C to
Note 4:
The LTC3897 is tested in a feedback loop that servos VFB to the 125°C operating junction temperature range are assured by design, output of the error amplifier while maintaining ITH at the midpoint of the characterization and correlation with statistical process controls. The current limit range. LTC3897I is guaranteed over the –40°C to 125°C operating junction
Note 5:
Dynamic supply current is higher due to the gate charge being temperature range. The LTC3897H is guaranteed over the –40°C to delivered at the switching frequency. 150°C operating temperature range. High junction temperatures degrade
Note 6:
Rise and fall times are measured using 10% and 90% levels. operation lifetime. Operation lifetime is derated for junction temperatures Delay times are measured using 50% levels. greater than 125°C. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating
Note 7:
See Minimum On-Time Considerations in the Applications conditions in conjunction with board layout, the rated package thermal Information section. impedance and other environmental factors. The junction temperature
Note 8:
Internal clamps limit the SG and DG pins to minimum of 10V (T above the CS pin. Driving these pins to voltages beyond the clamp may J, in °C) is calculated from the ambient temperature (TA, in °C) and power dissipation (P damage the device. D, in watts) according to the formula: T
Note 9:
Do not apply a voltage or current source to these pins. They must J = TA + (PD • θJA), where θJA = 34°C/W for the QFN package and where θ be connected to capacitive loads only, otherwise permanent damage may JA = 28°C/W for the FE package. occur. Rev. A 6 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Typical Application Related Parts