Datasheet LT8580 (Analog Devices) - 9

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APPLICATIONS INFORMATION Setting Output Voltage
For the SEPIC or dual inductor inverting topology (see Figure 1 and Figure 2): The output voltage is set by connecting a resistor (RFBX) from V V OUT to the FBX pin. RFBX is determined from the DC ≅ D + |VOUT| following equation: VIN + |VOUT| + VD − VCESAT |V R OUT − VFBX| The LT8580 can be used in configurations where the duty FBX = 83.3µA cycle is higher than DCMAX, but it must be operated in the discontinuous conduction mode so that the effective duty where VFBX is 1.204V (typical) for noninverting topologies cycle is reduced. (i.e., boost and SEPIC regulators) and 3mV (typical) for inverting topologies (see the Electrical Characteristics).
Inductor Selection Power Switch Duty Cycle
General Guidelines: The high frequency operation of the LT8580 allows for the use of small surface mount inductors. In order to maintain loop stability and deliver adequate For high efficiency, choose inductors with high frequency current to the load, the power NPN (Q1 in the Block Dia- core material, such as ferrite, to reduce core losses. To gram) cannot remain “on” for 100% of each clock cycle. improve efficiency, choose inductors with more volume The maximum allowable duty cycle is given by: for a given inductance. The inductor should have low (T DCR (copper wire resistance) to reduce I2R losses, and DC P − Min Off Time) MAX = • 100% must be able to handle the peak inductor current without TP saturating. Note that in some applications, the current where TP is the clock period and Min Off Time (found in handling requirements of the inductor can be lower, such the Electrical Characteristics) is typically 100ns. as in the SEPIC topology, where each inductor only carries The application should be designed so that the operating a fraction of the total switch current. Multilayer or chip duty cycle does not exceed DC inductors usually do not have enough core area to sup- MAX. port peak inductor currents in the 1A to 2A range. To The minimum allowable duty cycle is given by: minimize radiated noise, use a toroidal or shielded induc- Min On Time tor. Note that the inductance of shielded types will drop DCMIN = • 100% more as current increases, and will saturate more easily. TP See Table 1 for a list of inductor manufacturers. Thorough where TP is the clock period and Minimum On Time is as lab evaluation is recommended to verify that the following shown in the Typical Performance Characteristics. guidelines properly suit the final application.
Table 1. Inductor Manufacturers
The application should be designed so that the operating Coilcraft XAL5050, MSD7342, MSS7341 and www.coilcraft.com duty cycle is at least DCMIN. LPS4018 Series Duty cycle equations for several common topologies are Coiltronics DR, DRQ, LD and CD Series www.coiltronics.com given below, where VD is the diode forward voltage drop Sumida CDRH8D58/LD, CDRH64B, and www.sumida.com and V CDRH70D430MN Series CESAT is typically 400mV at 0.75A. Würth WE-PD, WE-DD, WE-TPC, www.we-online.com For the boost topology: WE-LHMI and WE-LQS Series V DC ≅ OUT − VIN + VD Minimum Inductance: Although there can be a trade-off VOUT + VD − VCESAT with efficiency, it is often desirable to minimize board space by choosing smaller inductors. When choosing Rev. B For more information www.analog.com 9 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts