Datasheet LT8580 (Analog Devices) - 6
| Hersteller | Analog Devices |
| Beschreibung | Boost/SEPIC/Inverting DC/DC Converter with 1A, 65V Switch, Soft-Start and Synchronization |
| Seiten / Seite | 32 / 6 — PIN FUNCTIONS. FBX (Pin 1):. RT (Pin 6):. SS (Pin 7):. VC (Pin 2):. SYNC … |
| Revision | B |
| Dateiformat / Größe | PDF / 1.4 Mb |
| Dokumentensprache | Englisch |
PIN FUNCTIONS. FBX (Pin 1):. RT (Pin 6):. SS (Pin 7):. VC (Pin 2):. SYNC (Pin 8):. IN (Pin 3):. SW (Pin 4):. SHDN (Pin 5):
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LT8580
PIN FUNCTIONS FBX (Pin 1):
Positive and Negative Feedback Pin. For a sequence. Drive below 1.21V to disable the chip. Drive noninverting or inverting converter, tie a resistor from the above 1.40V to activate the chip and restart the soft-start FBX pin to VOUT according to the following equations: sequence. Do not float this pin. (V
RT (Pin 6):
Timing Resistor Pin. Adjusts the switching R OUT − 1.204V) FBX = ; Noninverting Converter 83.3µA frequency. Place a resistor from this pin to ground to set the frequency to a fixed free running level. Do not float V R OUT + 3mV ( ) this pin. FBX = ; Inverting Converter 83.3µA
SS (Pin 7):
Soft-Start Pin. Place a soft-start capacitor here.
VC (Pin 2):
Error Amplifier Output Pin. Tie external com- Upon start-up, the SS pin will be charged by a (nominally) pensation network to this pin. 280k resistor to about 2.1V.
V SYNC (Pin 8):
To synchronize the switching frequency to
IN (Pin 3):
Input Supply Pin. Must be locally bypassed. an outside clock, simply drive this pin with a clock. The
SW (Pin 4):
Switch Pin. This is the collector of the internal high voltage level of the clock needs to exceed 1.3V, and NPN Power switch. Minimize the metal trace area connec- the low level should be less 0.4V. Drive this pin to less ted to this pin to minimize EMI. than 0.4V to revert to the internal free-running clock. See
SHDN (Pin 5):
Shutdown Pin. In conjunction with the the Applications Information section for more information. UVLO (undervoltage lockout) circuit, this pin is used
GND (Exposed Pad Pin 9):
Ground. Exposed pad must to enable/disable the chip and restart the soft-start be soldered directly to local ground plane.
BLOCK DIAGRAM
RC VIN CSS CC CIN 7 2 50k SS VC SHDN 5 – DISCHARGE L1 1.3V + DETECT 280k UVLO SW D1 SR2 VC SOFT- 4 V R OUT START ILIMIT COMPARATOR Q Q2 – SR1 DRIVER VIN S C1 A3 R Q Q1 3 1.204V REFERENCE + S + + RFBX 14.5k A1 ∑ A4 0.02Ω – – SLOPE COMPENSATION FBX GND 1 + 9 FREQUENCY ÷N ADJUSTABLE 14.5k A2 FOLDBACK OSCILLATOR – SYNC BLOCK SYNC RT 8 6 RT 8580 BD Rev. B 6 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts
PIN FUNCTIONS FBX (Pin 1):
Positive and Negative Feedback Pin. For a sequence. Drive below 1.21V to disable the chip. Drive noninverting or inverting converter, tie a resistor from the above 1.40V to activate the chip and restart the soft-start FBX pin to VOUT according to the following equations: sequence. Do not float this pin. (V
RT (Pin 6):
Timing Resistor Pin. Adjusts the switching R OUT − 1.204V) FBX = ; Noninverting Converter 83.3µA frequency. Place a resistor from this pin to ground to set the frequency to a fixed free running level. Do not float V R OUT + 3mV ( ) this pin. FBX = ; Inverting Converter 83.3µA
SS (Pin 7):
Soft-Start Pin. Place a soft-start capacitor here.
VC (Pin 2):
Error Amplifier Output Pin. Tie external com- Upon start-up, the SS pin will be charged by a (nominally) pensation network to this pin. 280k resistor to about 2.1V.
V SYNC (Pin 8):
To synchronize the switching frequency to
IN (Pin 3):
Input Supply Pin. Must be locally bypassed. an outside clock, simply drive this pin with a clock. The
SW (Pin 4):
Switch Pin. This is the collector of the internal high voltage level of the clock needs to exceed 1.3V, and NPN Power switch. Minimize the metal trace area connec- the low level should be less 0.4V. Drive this pin to less ted to this pin to minimize EMI. than 0.4V to revert to the internal free-running clock. See
SHDN (Pin 5):
Shutdown Pin. In conjunction with the the Applications Information section for more information. UVLO (undervoltage lockout) circuit, this pin is used
GND (Exposed Pad Pin 9):
Ground. Exposed pad must to enable/disable the chip and restart the soft-start be soldered directly to local ground plane.
BLOCK DIAGRAM
RC VIN CSS CC CIN 7 2 50k SS VC SHDN 5 – DISCHARGE L1 1.3V + DETECT 280k UVLO SW D1 SR2 VC SOFT- 4 V R OUT START ILIMIT COMPARATOR Q Q2 – SR1 DRIVER VIN S C1 A3 R Q Q1 3 1.204V REFERENCE + S + + RFBX 14.5k A1 ∑ A4 0.02Ω – – SLOPE COMPENSATION FBX GND 1 + 9 FREQUENCY ÷N ADJUSTABLE 14.5k A2 FOLDBACK OSCILLATOR – SYNC BLOCK SYNC RT 8 6 RT 8580 BD Rev. B 6 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts