Datasheet LTC3780 (Analog Devices) - 10

HerstellerAnalog Devices
BeschreibungHigh Efficiency, Synchronous, 4-Switch Buck-Boost Controller
Seiten / Seite30 / 10 — PIN FUNCTIONS (SSOP/QFN) PGOOD (Pin 1/Pin 30):. SS (Pin 2/Pin 31):. …
RevisionG
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DokumentenspracheEnglisch

PIN FUNCTIONS (SSOP/QFN) PGOOD (Pin 1/Pin 30):. SS (Pin 2/Pin 31):. PLLFLTR (Pin 10/Pin 8):. SENSE+ (Pin 3/Pin 1):

PIN FUNCTIONS (SSOP/QFN) PGOOD (Pin 1/Pin 30): SS (Pin 2/Pin 31): PLLFLTR (Pin 10/Pin 8): SENSE+ (Pin 3/Pin 1):

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PIN FUNCTIONS (SSOP/QFN) PGOOD (Pin 1/Pin 30):
Open-Drain Logic Output. PGOOD operation. When the pin is tied to INTVCC, the constant is pulled to ground when the output voltage is not within frequency discontinuous current mode is active in buck ±7.5% of the regulation point. or boost operation.
SS (Pin 2/Pin 31):
Soft-start reduces the input power
PLLFLTR (Pin 10/Pin 8):
The phase-locked loop’s sources’ surge currents by gradually increasing the lowpass filter is tied to this pin. Alternatively, this pin can controller’s current limit. A minimum value of 6.8nF is be driven with an AC or DC voltage source to vary the recommended on this pin. frequency of the internal oscillator.
SENSE+ (Pin 3/Pin 1):
The (+) Input to the Current Sense
PLLIN (Pin 11/Pin 10):
External Synchronization Input to and Reverse Current Detect Comparators. The ITH pin volt- Phase Detector. This pin is internally terminated to SGND age and built-in offsets between SENSE– and SENSE+ pins, with 50kΩ. The phase-locked loop will force the rising in conjunction with RSENSE, set the current trip threshold. bottom gate signal of the controller to be synchronized
SENSE– (Pin 4/Pin 2):
The (–) Input to the Current Sense with the rising edge of the PLLIN signal. and Reverse Current Detect Comparators.
STBYMD (Pin 12/Pin 11):
LDO Control Pin. Determines
I
whether the internal LDO remains active when the control-
TH (Pin 5/Pin 3):
Current Control Threshold and Error Amplifier Compensation Point. The current comparator ler is shut down. See Operation section for details. If the threshold increases with this control voltage. The voltage STBYMD pin is pulled to ground, the SS pin is internally ranges from 0V to 2.4V. pulled to ground, preventing start-up and thereby provid- ing a single control pin for turning off the controller. To
VOSENSE (Pin 6/Pin 4):
Error Amplifier Feedback Input. keep the LDO active when RUN is low, for example to This pin connects the error amplifier input to an external power a “wake up” circuit which controls the state of the resistor divider from VOUT. RUN pin, bypass STBYMD to signal ground with a 0.1µF
SGND (Pin 7/Pin 5, Exposed Pad Pin 33):
Signal Ground. All capacitor, or use a resistor divider from VIN to keep the small-signal components and compensation components pin within 2V to 5V. should connect to this ground, which should be connected
BOOST2, BOOST1 (Pins 13, 24/Pins 14, 27):
Boosted to PGND at a single point. The QFN exposed pad must be Floating Driver Supply. The (+) terminal of the bootstrap soldered to PCB ground for electrical connection and rated capacitor CA and CB (Figure 11) connects here. The BOOST2 thermal performance. pin swings from a diode voltage below INTVCC up to VIN
RUN (Pin 8/Pin 6):
Run Control Input. Forcing the RUN + INTVCC. The BOOST1 pin swings from a diode voltage pin below 1.5V causes the IC to shut down the switching below INTVCC up to VOUT + INTVCC. regulator circuitry. There is a 100k resistor between the
TG2, TG1 (Pins 14, 23/Pins 15, 26):
Top Gate Drive. Drives RUN pin and SGND in the IC. Do not apply >6V to this pin. the top N-channel MOSFET with a voltage swing equal to
FCB (Pin 9/Pin 7):
Forced Continuous Control Input. The INTVCC superimposed on the switch node voltage SW. voltage applied to this pin sets the operating mode of the
SW2, SW1 (Pins 15, 22/Pins 17, 24):
Switch Node. The (–) controller. When the applied voltage is less than 0.8V, the terminal of the bootstrap capacitor CA and CB (Figure 11) forced continuous current mode is active. When this pin connects here. The SW2 pin swings from a Schottky diode is allowed to float, the Burst Mode operation is active in (external) voltage drop below ground up to VIN. The SW1 boost operation and the skip-cycle mode is active in buck pin swings from a Schottky diode (external) voltage drop below ground up to VOUT. Rev G 10 For more information www.analog.com Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Block Diagram Operation Applications Information Typical Application Related Parts Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Package Description Revision History Typical Application Related Parts