Datasheet PIC18F242, PIC18F252, PIC18F442, PIC18F452 (Microchip) - 4

PIC18FXX2 Pin Diagrams
+ - F F RE RE /V /V PP
PLCC
/V /AN3 /AN2 /AN1 /AN0 R L /PGD /PGC /PGM RA3 RA2 RA1 RA0 MC NC RB7 RB6 RB5 RB4 NC 6 5 4 3 2 1 44 43 42 41 40 RA4/T0CKI 7 39 RB3/CCP2* RA5/AN4/SS/LVDIN 8 38 RB2/INT2 RE0/RD/AN5 9 37 RB1/INT1 RE1/WR/AN6 10 36
PIC18F442
RB0/INT0 RE2/CS/AN7 11 35 VDD VDD 12 34 VSS
PIC18F452
13 33 RD7/PSP7 VSS 14 32 OSC1/CLKI RD6/PSP6 15 31 OSC2/CLKO/RA6 RD5/PSP5 RC0/T1OSO/T1CKI 16 30 RD4/PSP4 1718 19 20 21 22 23 24 25 26 27 28 NC 29 RC7/RX/DT RC1 RC2 RC3 RD0 RD1 RD2 RD3 RC4 RC5 RC6 NC /T /CCP1 /SCK /PS /PS /PS /PS /SDI/SDA /SDO /T 1 X/CK O P P P P SI/CCP2 / 0 1 2 3 S C L * * L C 3 2 1 0 /S SI/CCP2 P P P P O X/CK DO DI/SDA S S S S CK 1 /T /S /S /P /P /P /P /S /CCP1 /T RC6 RC5 RC4 RD3 RD2 RD1 RD0 RC3 RC2 RC1 NC
TQFP
44 43 42 41 40 39 38 37 36 35 34 RC7/RX/DT 1 33 NC RD4/PSP4 2 32 RC0/T1OSO/T1CKI RD5/PSP5 3 31 OSC2/CLKO/RA6 RD6/PSP6 4 30 OSC1/CLKI RD7/PSP7 5
PIC18F442
29 VSS VSS 6 28 VDD VDD 7
PIC18F452
27 RE2/AN7/CS RB0/INT0 8 26 RE1/AN6/WR RB1/INT1 9 25 RE0/AN5/RD RB2/INT2 10 24 RA5/AN4/SS/LVDIN RB3/CCP2* 11 12 13 14 15 16 17 18 19 20 21 22 23 RA4/T0CKI NC NC RB4 RB5 RB6 RB7 MC RA0 RA1 R R A A L 2/A 3/A / / / PGM PGC PGD R / / AN0 AN1 /V N N PP 2/ 3/ V V RE RE F F - + * RB3 is the alternate pin for the CCP2 pin multiplexing. DS39564C-page 2 © 2006 Microchip Technology Inc. Document Outline High Performance RISC CPU: Peripheral Features: Peripheral Features (Continued): Analog Features: Special Microcontroller Features: CMOS Technology: Pin Diagrams Pin Diagrams (Cont.’d) Table of Contents Most Current Data Sheet Errata Customer Notification System 1.0 Device Overview TABLE 1-1: Device Features FIGURE 1-1: PIC18F2X2 Block Diagram FIGURE 1-2: PIC18F4X2 Block Diagram TABLE 1-2: PIC18f2x2 Pinout I/O Descriptions TABLE 1-3: PIC18F4x2 Pinout I/O Descriptions 2.0 Oscillator Configurations 2.1 Oscillator Types 2.2 Crystal Oscillator/Ceramic Resonators FIGURE 2-1: Crystal/Ceramic Resonator Operation (HS, XT or LP Configuration) TABLE 2-1: Capacitor Selection for Ceramic Resonators TABLE 2-2: Capacitor Selection for Crystal Oscillator FIGURE 2-2: External Clock Input Operation (HS, XT or LP OSC Configuration) 2.3 RC Oscillator FIGURE 2-3: RC Oscillator Mode 2.4 External Clock Input FIGURE 2-4: External Clock Input Operation (EC Configuration) FIGURE 2-5: External Clock Input Operation (ECIO Configuration) 2.5 HS/PLL FIGURE 2-6: PLL Block Diagram 2.6 Oscillator Switching Feature FIGURE 2-7: Device Clock Sources 2.6.1 System clock switch bit 2.6.2 Oscillator Transitions FIGURE 2-8: Timing Diagram For Transition From OSC1 to Timer1 Oscillator FIGURE 2-9: Timing For Transition Between Timer1 and OSC1 (HS, XT, LP) FIGURE 2-10: Timing For Transition Between Timer1 and OSC1 (HS with PLL) FIGURE 2-11: Timing For Transition Between Timer1 and OSC1 (RC, EC) 2.7 Effects of SLEEP Mode on the On-Chip Oscillator TABLE 2-3: OSC1 and OSC2 Pin States in Sleep Mode 2.8 Power-up Delays 3.0 Reset FIGURE 3-1: Simplified Block Diagram of On-chip Reset Circuit 3.1 Power-On Reset (POR) FIGURE 3-2: External Power-on Reset Circuit (for Slow Vdd Power-up) 3.2 Power-up Timer (PWRT) 3.3 Oscillator Start-up Timer (OST) 3.4 PLL Lock Time-out 3.5 Brown-out Reset (BOR) 3.6 Time-out Sequence TABLE 3-1: Time-out in Various Situations TABLE 3-2: Status Bits, Their Significance and the Initialization Condition for RCON Register TABLE 3-3: Initialization Conditions for All Registers FIGURE 3-3: Time-out Sequence on Power-up (MCLR Tied to Vdd) FIGURE 3-4: Time-out Sequence on Power-up (MCLR not Tied to Vdd): Case 1 FIGURE 3-5: Time-out Sequence on Power-up (MCLR not Tied to Vdd): Case 2 FIGURE 3-6: Slow Rise Time (MCLR Tied to Vdd) FIGURE 3-7: Time-out Sequence on POR w/ PLL Enabled (MCLR tied to Vdd) 4.0 Memory Organization 4.1 Program Memory Organization FIGURE 4-1: Program Memory Map and Stack for PIC18F442/242 FIGURE 4-2: Program Memory Map and Stack for PIC18F452/252 4.2 Return Address Stack 4.2.1 Top-Of-Stack Access 4.2.2 Return Stack Pointer (STKPTR) FIGURE 4-3: Return Address Stack and Associated Registers 4.2.3 PUSH and POP instructions 4.2.4 Stack Full/Underflow Resets 4.3 Fast Register Stack 4.4 PCL, PCLATH and PCLATU 4.5 Clocking Scheme/Instruction Cycle FIGURE 4-4: Clock/Instruction Cycle 4.6 Instruction Flow/Pipelining 4.7 Instructions in Program Memory FIGURE 4-5: Instructions in Program memory 4.7.1 Two-Word Instructions 4.8 Lookup Tables 4.8.1 Computed GOTO 4.8.2 Table reads/Table writes 4.9 Data Memory Organization 4.9.1 General purpose Register File 4.9.2 Special Function Registers FIGURE 4-6: Data Memory Map for PIC18F242/442 FIGURE 4-7: Data Memory Map for PIC18F252/452 TABLE 4-1: Special Function Register Map TABLE 4-2: Register File Summary 4.10 Access Bank 4.11 Bank Select Register (BSR) FIGURE 4-8: Direct Addressing 4.12 Indirect Addressing, INDF and FSR Registers 4.12.1 Indirect Addressing Operation FIGURE 4-9: Indirect Addressing Operation FIGURE 4-10: Indirect Addressing 4.13 STATUS Register 4.14 RCON Register 5.0 FLASH Program Memory 5.1 Table Reads and Table Writes FIGURE 5-1: Table Read Operation FIGURE 5-2: Table Write Operation 5.2 Control Registers 5.2.1 EECON1 AND EECON2 REGISTERS 5.2.2 TABLAT - Table Latch Register 5.2.3 TBLPTR - Table Pointer Register 5.2.4 TABLE POINTER BOUNDARIES TABLE 5-1: Table Pointer Operations with TBLRD and TBLWT Instructions FIGURE 5-3: TABLE POINTER BOUNDARIES BASED ON OPERATION 5.3 Reading the FLASH Program Memory FIGURE 5-4: Reads from FLASH Program Memory 5.4 Erasing FLASH Program memory 5.4.1 FLASH PROGRAM MEMORY ERASE SEQUENCE 5.5 Writing to FLASH Program Memory FIGURE 5-5: TABLE WRITES to flash PROGRAM MEMORY 5.5.1 FLASH Program memory write sequence 5.5.2 Write verify 5.5.3 unexpected termination of write operation 5.5.4 protection against spurious writes 5.6 FLASH Program Operation During Code Protection TABLE 5-2: Registers Associated with program flash Memory 6.0 Data EEPROM Memory 6.1 EEADR 6.2 EECON1 and EECON2 Registers 6.3 Reading the Data EEPROM Memory 6.4 Writing to the Data EEPROM Memory 6.5 Write Verify 6.6 Protection Against Spurious Write 6.7 Operation During Code Protect 6.8 Using the Data EEPROM TABLE 6-1: Registers Associated with DATA EEPROM Memory 7.0 8 X 8 Hardware Multiplier 7.1 Introduction TABLE 7-1: Performance Comparison 7.2 Operation 8.0 Interrupts FIGURE 8-1: Interrupt Logic 8.1 INTCON Registers 8.2 PIR Registers 8.3 PIE Registers 8.4 IPR Registers 8.5 RCON Register 8.6 INT0 Interrupt 8.7 TMR0 Interrupt 8.8 PORTB Interrupt-on-Change 8.9 Context Saving During Interrupts 9.0 I/O Ports 9.1 PORTA, TRISA and LATA Registers FIGURE 9-1: Block Diagram of RA3:RA0 and RA5 Pins FIGURE 9-2: Block Diagram of RA4/T0CKI Pin FIGURE 9-3: Block Diagram of RA6 PIN TABLE 9-1: PORTA Functions TABLE 9-2: Summary of Registers Associated with PORTA 9.2 PORTB, TRISB and LATB Registers FIGURE 9-4: Block Diagram of RB7:RB4 Pins FIGURE 9-5: Block Diagram of RB2:RB0 Pins FIGURE 9-6: Block Diagram of RB3 PIN TABLE 9-3: PORTB Functions TABLE 9-4: Summary of Registers Associated with PORTB 9.3 PORTC, TRISC and LATC Registers FIGURE 9-7: PORTC Block Diagram (Peripheral Output Override) TABLE 9-5: PORTC Functions TABLE 9-6: Summary of Registers Associated with PORTC 9.4 PORTD, TRISD and LATD Registers FIGURE 9-8: PORTD Block Diagram in I/O Port Mode TABLE 9-7: PORTD Functions TABLE 9-8: Summary of Registers Associated with PORTD 9.5 PORTE, TRISE and LATE Registers FIGURE 9-9: PORTE Block Diagram in I/O Port Mode TABLE 9-9: PORTE Functions TABLE 9-10: Summary of Registers Associated with PORTE 9.6 Parallel Slave Port FIGURE 9-10: PORTD and PORTE Block Diagram (Parallel Slave Port) FIGURE 9-11: Parallel Slave Port Write Waveforms FIGURE 9-12: Parallel Slave Port Read Waveforms TABLE 9-11: Registers Associated with Parallel Slave Port 10.0 Timer0 Module FIGURE 10-1: Timer0 Block Diagram in 8-bit Mode FIGURE 10-2: Timer0 Block Diagram in 16-bit Mode 10.1 Timer0 Operation 10.2 Prescaler 10.2.1 Switching Prescaler Assignment 10.3 Timer0 Interrupt 10.4 16-Bit Mode Timer Reads and Writes TABLE 10-1: Registers Associated with Timer0 11.0 Timer1 Module 11.1 Timer1 Operation FIGURE 11-1: Timer1 Block Diagram FIGURE 11-2: Timer1 Block Diagram: 16-bit Read/Write Mode 11.2 Timer1 Oscillator TABLE 11-1: Capacitor Selection for the alternate Oscillator 11.3 Timer1 Interrupt 11.4 Resetting Timer1 using a CCP Trigger Output 11.5 Timer1 16-Bit Read/Write Mode TABLE 11-2: Registers Associated with Timer1 as a Timer/Counter 12.0 Timer2 Module 12.1 Timer2 Operation 12.2 Timer2 Interrupt 12.3 Output of TMR2 FIGURE 12-1: Timer2 Block Diagram TABLE 12-1: Registers Associated with Timer2 as a Timer/Counter 13.0 Timer3 Module 13.1 Timer3 Operation FIGURE 13-1: Timer3 Block Diagram FIGURE 13-2: Timer3 Block Diagram Configured in 16-bit READ/WRITE Mode 13.2 Timer1 Oscillator 13.3 Timer3 Interrupt 13.4 Resetting Timer3 Using a CCP Trigger Output TABLE 13-1: Registers Associated with Timer3 as a Timer/Counter 14.0 Capture/Compare/PWM (CCP) Modules 14.1 CCP1 Module TABLE 14-1: CCP Mode - Timer Resource 14.2 CCP2 Module TABLE 14-2: Interaction of Two CCP Modules 14.3 Capture Mode 14.3.1 CCP pin Configuration 14.3.2 Timer1/Timer3 Mode Selection 14.3.3 Software Interrupt 14.3.4 CCP Prescaler FIGURE 14-1: Capture Mode Operation Block Diagram 14.4 Compare Mode 14.4.1 CCP Pin Configuration 14.4.2 timer1/Timer3 Mode Selection 14.4.3 Software Interrupt Mode 14.4.4 Special Event Trigger FIGURE 14-2: Compare Mode Operation Block Diagram TABLE 14-3: Registers Associated with Capture, compare, Timer1 and Timer3 14.5 PWM Mode FIGURE 14-3: Simplified PWM Block Diagram FIGURE 14-4: PWM Output 14.5.1 PWM period 14.5.2 PWM Duty Cycle 14.5.3 SetUp for PWM Operation TABLE 14-4: Example PWM Frequencies and Resolutions at 40 MHz TABLE 14-5: Registers Associated with PWM and Timer2 15.0 Master Synchronous Serial Port (MSSP) Module 15.1 Master SSP (MSSP) Module Overview 15.2 Control Registers 15.3 SPI Mode FIGURE 15-1: MSSP Block Diagram (SPIMode) 15.3.1 Registers 15.3.2 Operation 15.3.3 Enabling SPI I/O 15.3.4 Typical Connection FIGURE 15-2: SPI Master/Slave Connection 15.3.5 Master Mode FIGURE 15-3: SPI Mode Waveform (Master Mode) 15.3.6 Slave Mode 15.3.7 Slave Select Synchronization FIGURE 15-4: Slave Synchronization Waveform FIGURE 15-5: SPI Mode Waveform (Slave Mode with CKE = 0) FIGURE 15-6: SPI Mode Waveform (Slave Mode with CKE = 1) 15.3.8 Sleep Operation 15.3.9 Effects of a Reset 15.3.10 Bus Mode Compatibility TABLE 15-1: SPI Bus Modes TABLE 15-2: Registers Associated with SPI Operation 15.4 I2C Mode FIGURE 15-7: MSSP Block Diagram (I2C Mode) 15.4.1 Registers 15.4.2 Operation 15.4.3 SLAVE Mode FIGURE 15-8: I2C Slave Mode Timing with SEN = 0 (Reception, 7-bit Address) FIGURE 15-9: I2C Slave Mode Timing (Transmission, 7-bit Address) FIGURE 15-10: I2C Slave Mode Timing with SEN = 0 (Reception, 10-bit Address) FIGURE 15-11: I2C Slave Mode Timing (Transmission, 10-bit Address) 15.4.4 Clock Stretching FIGURE 15-12: Clock synchronization Timing FIGURE 15-13: I2C Slave Mode Timing With SEN = 1 (Reception, 7-bit Address) FIGURE 15-14: I2C Slave Mode Timing SEN = 1 (Reception, 10-bit Address) 15.4.5 General Call Address Support FIGURE 15-15: Slave Mode General Call Address Sequence (7 or 10-bit Address Mode) 15.4.6 Master Mode FIGURE 15-16: MSSP Block Diagram (I2C Master Mode) 15.4.7 Baud Rate Generator FIGURE 15-17: Baud Rate Generator Block Diagram TABLE 15-3: I2C Clock Rate w/BRG FIGURE 15-18: Baud Rate Generator Timing With Clock Arbitration 15.4.8 I2C Master Mode Start Condition Timing FIGURE 15-19: First Start Bit Timing 15.4.9 I2C Master Mode Repeated Start Condition Timing FIGURE 15-20: Repeat Start Condition Waveform 15.4.10 I2C Master Mode Transmission 15.4.11 I2C Master Mode Reception FIGURE 15-21: I2C Master Mode Waveform (Transmission, 7 or 10-bit Address) FIGURE 15-22: I2C Master Mode Waveform (Reception, 7-Bit Address) 15.4.12 Acknowledge Sequence Timing 15.4.13 Stop Condition Timing FIGURE 15-23: Acknowledge Sequence Waveform FIGURE 15-24: Stop Condition Receive or Transmit Mode 15.4.14 Sleep Operation 15.4.15 Effect of a Reset 15.4.16 Multi-Master Mode 15.4.17 Multi -Master Communication, Bus Collision, and Bus Arbitration FIGURE 15-25: Bus Collision Timing for Transmit and Acknowledge FIGURE 15-26: Bus Collision During Start Condition (SDA only) FIGURE 15-27: Bus Collision During Start Condition (SCL = 0) FIGURE 15-28: BRG Reset Due to SDA Arbitration During Start Condition FIGURE 15-29: Bus Collision During a Repeated Start Condition (Case 1) FIGURE 15-30: Bus Collision During Repeated Start Condition (Case 2) FIGURE 15-31: Bus Collision During a STOP Condition (Case 1) FIGURE 15-32: Bus Collision During a STOP Condition (Case 2) 16.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART) 16.1 USART Baud Rate Generator (BRG) 16.1.1 SAMPLING TABLE 16-1: Baud Rate Formula TABLE 16-2: Registers Associated with Baud Rate Generator TABLE 16-3: Baud Rates for Synchronous Mode TABLE 16-4: Baud Rates for Asynchronous Mode (BRGH = 0) TABLE 16-5: Baud Rates for Asynchronous Mode (BRGH = 1) 16.2 USART Asynchronous Mode 16.2.1 USART Asynchronous Transmitter FIGURE 16-1: USART Transmit Block Diagram FIGURE 16-2: Asynchronous Transmission FIGURE 16-3: Asynchronous Transmission (Back to Back) TABLE 16-6: Registers Associated with Asynchronous Transmission 16.2.2 USART Asynchronous Receiver 16.2.3 Setting up 9-bit mode with address detect FIGURE 16-4: USART Receive Block Diagram FIGURE 16-5: Asynchronous Reception TABLE 16-7: Registers Associated with Asynchronous Reception 16.3 USART Synchronous Master Mode 16.3.1 USART Synchronous Master Transmission TABLE 16-8: Registers Associated with Synchronous Master Transmission FIGURE 16-6: Synchronous Transmission FIGURE 16-7: Synchronous Transmission (Through TXEN) 16.3.2 USART Synchronous Master Reception TABLE 16-9: Registers Associated with Synchronous Master Reception FIGURE 16-8: Synchronous Reception (Master Mode, SREN) 16.4 USART Synchronous Slave Mode 16.4.1 USART Synchronous Slave Transmit TABLE 16-10: Registers Associated with Synchronous Slave Transmission 16.4.2 USART Synchronous Slave Reception TABLE 16-11: Registers Associated with Synchronous Slave Reception 17.0 Compatible 10-bit Analog-to-Digital Converter (A/D) Module FIGURE 17-1: A/D Block Diagram 17.1 A/D Acquisition Requirements FIGURE 17-2: Analog Input Model 17.2 Selecting the A/D Conversion Clock 17.3 Configuring Analog Port Pins TABLE 17-1: Tad vs. Device Operating Frequencies 17.4 A/D Conversions FIGURE 17-3: A/D Conversion Tad Cycles 17.4.1 A/D Result Registers FIGURE 17-4: A/D Result Justification 17.5 Use of the CCP2 Trigger TABLE 17-2: Summary of A/D Registers 18.0 Low Voltage Detect FIGURE 18-1: Typical Low Voltage Detect Application FIGURE 18-2: Low Voltage Detect (LVD) Block Diagram FIGURE 18-3: LOW VOLTAGE DETECT (LVD) WITH EXTERNAL INPUT BLOCK DIAGRAM 18.1 Control Register 18.2 Operation FIGURE 18-4: Low Voltage Detect waveforms 18.2.1 Reference Voltage Set Point 18.2.2 Current Consumption 18.3 Operation During SLEEP 18.4 Effects of a RESET 19.0 Special Features of the CPU 19.1 Configuration Bits TABLE 19-1: Configuration bits and Device IDs 19.2 Watchdog Timer (WDT) 19.2.1 Control Register 19.2.2 WDT Postscaler FIGURE 19-1: Watchdog Timer Block Diagram TABLE 19-2: Summary of Watchdog Timer Registers 19.3 Power-down Mode (SLEEP) 19.3.1 Wake-up from SLEEP 19.3.2 Wake-Up Using Interrupts FIGURE 19-2: Wake-up from Sleep Through Interrupt(1,2) 19.4 Program Verification and Code Protection FIGURE 19-3: Code Protected program memory FOR PIC18F2XX/4XX TABLE 19-3: Summary of Code Protection Registers 19.4.1 Program Memory code Protection FIGURE 19-4: Table Write (WRTn) Disallowed FIGURE 19-5: External Block Table Read (EBTRn) Disallowed FIGURE 19-6: External Block Table Read (EBTRn) Allowed 19.4.2 Data EEPROM Code Protection 19.4.3 Configuration Register Protection 19.5 ID Locations 19.6 In-Circuit Serial Programming 19.7 In-Circuit Debugger TABLE 19-4: Debugger Resources 19.8 Low Voltage ICSP Programming 20.0 Instruction Set Summary TABLE 20-1: Opcode Field Descriptions FIGURE 20-1: General Format for Instructions TABLE 20-2: PIC18FXXX Instruction Set 20.1 Instruction Set 21.0 Development Support 21.1 MPLAB Integrated Development Environment Software 21.2 MPASM Assembler 21.3 MPLAB C17 and MPLAB C18 C Compilers 21.4 MPLINK Object Linker/ MPLIB Object Librarian 21.5 MPLAB SIM Software Simulator 21.6 MPLAB ICE High Performance Universal In-Circuit Emulator with MPLAB IDE 21.7 ICEPIC In-Circuit Emulator 21.8 MPLAB ICD In-Circuit Debugger 21.9 PRO MATE II Universal Device Programmer 21.10 PICSTART Plus Entry Level Development Programmer 21.11 PICDEM 1 Low Cost PICmicro Demonstration Board 21.12 PICDEM 2 Low Cost PIC16CXX Demonstration Board 21.13 PICDEM 3 Low Cost PIC16CXXX Demonstration Board 21.14 PICDEM 17 Demonstration Board 21.15 KeeLoq Evaluation and Programming Tools TABLE 21-1: DEVELOPMENT TOOLS FROM MICROCHIP 22.0 Electrical Characteristics FIGURE 22-1: PIC18Fxx2 Voltage-Frequency Graph (Industrial) FIGURE 22-2: PIC18LFXX2 Voltage-Frequency Graph (Industrial) 22.1 DC Characteristics: PIC18FXX2 (Industrial, Extended) PIC18LFXX2 (Industrial) 22.2 DC Characteristics: PIC18FXX2 (Industrial, Extended) PIC18LFXX2 (Industrial) FIGURE 22-3: Low Voltage Detect Characteristics TABLE 22-1: Low Voltage Detect Characteristics TABLE 22-2: Memory Programming Requirements 22.3 AC (Timing) Characteristics 22.3.1 Timing Parameter Symbology 22.3.2 Timing Conditions TABLE 22-3: Temperature and Voltage Specifications - AC FIGURE 22-4: Load Conditions for Device Timing Specifications 22.3.3 Timing Diagrams and Specifications FIGURE 22-5: External Clock Timing (All Modes Except PLL) TABLE 22-4: External Clock Timing Requirements TABLE 22-5: PLL Clock Timing Specifications (Vdd = 4.2 to 5.5V) FIGURE 22-6: CLKO and I/O Timing TABLE 22-6: CLKO and I/O Timing Requirements FIGURE 22-7: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing FIGURE 22-8: Brown-out Reset Timing TABLE 22-7: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset ... FIGURE 22-9: Timer0 and Timer1 External Clock Timings TABLE 22-8: Timer0 and Timer1 External Clock Requirements FIGURE 22-10: Capture/Compare/PWM Timings (CCP1 and CCP2) TABLE 22-9: Capture/Compare/PWM Requirements (CCP1 and CCP2) FIGURE 22-11: Parallel Slave Port Timing (PIC18F4X2) TABLE 22-10: Parallel Slave Port Requirements (PIC18F4X2) FIGURE 22-12: Example SPI Master Mode Timing (CKE=0) TABLE 22-11: Example SPI Mode Requirements (Master Mode, CKE=0) FIGURE 22-13: Example SPI Master Mode Timing (CKE=1) TABLE 22-12: Example SPI Mode Requirements (Master Mode, CKE=1) FIGURE 22-14: Example SPI Slave Mode Timing (CKE=0) TABLE 22-13: Example SPI Mode Requirements (Slave Mode Timing (CKE=0)) FIGURE 22-15: Example SPI Slave Mode Timing (CKE=1) TABLE 22-14: Example SPI Slave Mode Requirements (CKE=1) FIGURE 22-16: I2C Bus Start/Stop Bits Timing TABLE 22-15: I2C Bus Start/Stop Bits Requirements (Slave Mode) FIGURE 22-17: I2C Bus Data Timing TABLE 22-16: I2C Bus Data Requirements (Slave Mode) FIGURE 22-18: Master SSP I2C Bus Start/Stop Bits Timing Waveforms TABLE 22-17: Master SSP I2C Bus Start/Stop Bits Requirements FIGURE 22-19: Master SSP I2C Bus Data Timing TABLE 22-18: Master SSP I2C Bus Data Requirements FIGURE 22-20: USART Synchronous Transmission (Master/Slave) Timing TABLE 22-19: USART Synchronous Transmission Requirements FIGURE 22-21: USART Synchronous Receive (Master/Slave) Timing TABLE 22-20: USART Synchronous Receive Requirements TABLE 22-21: A/D Converter Characteristics: PIC18FXX2 (Industrial, Extended) PIC18LFXX2 (Industrial) FIGURE 22-22: A/D Conversion Timing TABLE 22-22: A/D Conversion Requirements 23.0 DC and AC Characteristics Graphs and Tables FIGURE 23-1: Typical Idd vs. Fosc OVER Vdd (HS Mode) FIGURE 23-2: Maximum Idd vs. Fosc OVER Vdd (HS Mode) FIGURE 23-3: Typical Idd vs. Fosc OVER Vdd (HS/PLL Mode) FIGURE 23-4: Maximum Idd vs. Fosc over Vdd (HS/PLL Mode) FIGURE 23-5: Typical Idd vs. Fosc OVER Vdd (XT Mode) FIGURE 23-6: Maximum Idd vs. Fosc OVER Vdd (XT Mode) FIGURE 23-7: Typical Idd vs. Fosc OVER Vdd (LP Mode) FIGURE 23-8: Maximum Idd vs. Fosc OVER Vdd (LP Mode) FIGURE 23-9: Typical Idd vs. Fosc OVER Vdd (EC Mode) FIGURE 23-10: Maximum Idd vs. Fosc over Vdd (EC Mode) FIGURE 23-11: TYPICAL AND MAXIMUM Idd vs. Vdd (TIMER1 AS MAIN OSCILLATOR, 32.768kHz, C1 AND C2 =... FIGURE 23-12: Average Fosc vs. Vdd for Various Values of R (RC Mode, C = 20pF, +25°C) FIGURE 23-13: Average Fosc vs. Vdd for Various Values of R (RC Mode, C = 100pF, +25°C) FIGURE 23-14: Average Fosc vs. Vdd for Various Values of R (RC Mode, C = 300pF, +25°C) FIGURE 23-15: Ipd vs. Vdd, -40°C to +125°C (Sleep Mode, all peripherals disabled) FIGURE 23-16: DIbor vs. Vdd over Temperature (BOR Enabled, Vbor = 2.00 - 2.16V) FIGURE 23-17: Typical and Maximum DItmr1 vs. Vdd over Temperature (-10°C TO +70°C, Timer1 with Os... FIGURE 23-18: Typical and Maximum DIwdt vs. Vdd over Temperature (WDT enabled) FIGURE 23-19: Typical, Minimum and Maximum WDT Period vs. Vdd (-40°C to +125°C) FIGURE 23-20: DIlvd vs. Vdd over Temperature (lvd ENABLED, Vlvd = 4.5 - 4.78V) FIGURE 23-21: Typical, Minimum and Maximum Voh vs. Ioh (Vdd = 5V, -40°C to +125°C) FIGURE 23-22: Typical, Minimum and Maximum Voh vs. Ioh (Vdd = 3V, -40°C to +125°C) FIGURE 23-23: Typical and Maximum Vol vs. Iol (Vdd = 5V, -40°C to +125°C) FIGURE 23-24: Typical and Maximum Vol vs. Iol (Vdd = 3V, -40°C to +125°C) FIGURE 23-25: Minimum and Maximum Vin vs. Vdd (ST Input, -40°C to +125°C) FIGURE 23-26: Minimum and Maximum Vin vs. Vdd (TTL Input, -40°C to +125°C) FIGURE 23-27: Minimum and Maximum Vin vs. Vdd (I2C Input, -40°C to +125°C) FIGURE 23-28: A/D Non-linearity vs. Vrefh (Vdd = Vrefh, -40°C to +125°C) FIGURE 23-29: A/D Non-linearity vs. Vrefh (Vdd = 5V, -40°C to +125°C) 24.0 Packaging Information 24.1 Package Marking Information Package Marking Information (Cont’d) 24.2 Package Details 28-Lead Skinny Plastic Dual In-line (SP) – 300 mil Body (PDIP) 28-Lead Plastic Small Outline (SO) –Wide, 300 mil Body (SOIC) 40-Lead Plastic Dual In-line (P) – 600 mil Body (PDIP) 44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP) 44-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC) Appendix A: Revision History Revision A (June 2001) Revision B (August 2002) Revision C (October 2006) Appendix B: Device Differences TABLE B-1: Device Differences Appendix C: Conversion Considerations Appendix D: Migration from Baseline to Enhanced Devices Appendix E: Migration from Mid-range to Enhanced Devices Appendix F: Migration from High-end to Enhanced Devices INDEX The Microchip Web Site Customer Change Notification Service Customer Support Reader Response PIC18FXX2 Product Identification System Worldwide Sales and Service