Datasheet PIC16F870, PIC16F871 (Microchip) - 3

PIC16F870/871 Key Features PICmicroTM Mid-Range MCU Family Reference Manual PIC16F870 PIC16F871 (DS33023)
Operating Frequency DC - 20 MHz DC - 20 MHz RESETS (and Delays) POR, BOR (PWRT, OST) POR, BOR (PWRT, OST) FLASH Program Memory (14-bit words) 2K 2K Data Memory (bytes) 128 128 EEPROM Data Memory 64 64 Interrupts 10 11 I/O Ports Ports A,B,C Ports A,B,C,D,E Timers 3 3 Capture/Compare/PWM modules 1 1 Serial Communications USART USART Parallel Communications — PSP 10-bit Analog-to-Digital Module 5 input channels 8 input channels Instruction Set 35 Instructions 35 Instructions  2000-2013 Microchip Technology Inc. DS30569C-page 3 Document Outline Devices Included in this Data Sheet: Microcontroller Core Features: Pin Diagram Peripheral Features: Pin Diagrams Table of Contents Most Current Data Sheet Errata Customer Notification System 1.0 Device Overview FIGURE 1-1: PIC16F870 Block Diagram FIGURE 1-2: PIC16F871 Block Diagram TABLE 1-1: PIC16F870 Pinout Description TABLE 1-2: PIC16F871 Pinout Description 2.0 Memory Organization 2.1 Program Memory Organization FIGURE 2-1: PIC16F870/871 Program Memory Map and Stack 2.2 Data Memory Organization 2.2.1 General purpose Register File FIGURE 2-2: PIC16F870/871 Register File Map 2.2.2 Special Function Registers TABLE 2-1: Special Function Register Summary Register 2-1: Status Register (Address: 03h, 83h, 103h, 183h) Register 2-2: OPTION_REG Register (Address: 81h,181H) Register 2-3: INTCON Register (Address: 0Bh, 8Bh, 10Bh, 18Bh) Register 2-4: PIE1 Register (Address: 8CH) Register 2-5: PIR1 Register (Address: 0CH) Register 2-6: PIE2 Register (Address: 8DH) Register 2-7: PIR2 Register (Address: 0DH) Register 2-8: PCON Register (Address: 8EH) 2.3 PCL and PCLATH FIGURE 2-3: Loading of PC In Different Situations 2.3.1 computed GOTO 2.3.2 Stack 2.4 Program Memory Paging 2.5 Indirect Addressing, INDF and FSR Registers EXAMPLE 2-1: Indirect Addressing FIGURE 2-4: Direct/Indirect Addressing 3.0 Data EEPROM and Flash Program Memory 3.1 EEADR 3.2 EECON1 and EECON2 Registers Register 3-1: EECON1 Register (Address: 18Ch) 3.3 Reading the EEPROM Data Memory EXAMPLE 3-1: EEPROM DATA READ 3.4 Writing to the EEPROM Data Memory EXAMPLE 3-2: EEPROM DATA WRITE 3.5 Reading the FLASH Program Memory EXAMPLE 3-3: FLASH PROGRAM READ 3.6 Writing to the FLASH Program Memory EXAMPLE 3-4: FLASH PROGRAM WRITE 3.7 Write Verify 3.8 Protection Against Spurious Writes 3.9 Operation While Code Protected 3.10 FLASH Program Memory Write Protection TABLE 3-1: Read/Write State of Internal FLASH Program memory TABLE 3-2: Registers Associated with DATA EEPROM/PROGRAM FLASH 4.0 I/O Ports 4.1 PORTA and the TRISA Register EXAMPLE 4-1: Initializing PORTA FIGURE 4-1: Block Diagram of RA3:RA0 and RA5 Pins FIGURE 4-2: Block Diagram of RA4/T0CKI Pin TABLE 4-1: PORTA Functions TABLE 4-2: Summary of Registers Associated with PORTA 4.2 PORTB and the TRISB Register FIGURE 4-3: Block Diagram of RB3:RB0 Pins FIGURE 4-4: Block Diagram of RB7:RB4 Pins TABLE 4-3: PORTB Functions TABLE 4-4: Summary of Registers Associated with PORTB 4.3 PORTC and the TRISC Register FIGURE 4-5: PORTC Block Diagram (Peripheral Output Override) TABLE 4-5: PORTC Functions TABLE 4-6: Summary of Registers Associated with PORTC 4.4 PORTD and TRISD Registers FIGURE 4-6: PORTD Block Diagram (in I/O Port Mode) TABLE 4-7: PORTD Functions TABLE 4-8: Summary of Registers Associated with PORTD 4.5 PORTE and TRISE Register FIGURE 4-7: PORTE Block Diagram (in I/O Port Mode) Register 4-1: TRISE Register (Address: 89H) TABLE 4-9: PORTE Functions TABLE 4-10: Summary of Registers Associated with PORTE 4.6 Parallel Slave Port FIGURE 4-8: PORTD and PORTE Block Diagram (Parallel Slave Port) FIGURE 4-9: Parallel Slave Port Write Waveforms FIGURE 4-10: Parallel Slave Port Read Waveforms TABLE 4-11: Registers Associated with Parallel Slave Port 5.0 Timer0 Module 5.1 Timer0 Interrupt FIGURE 5-1: Block Diagram of the Timer0/WDT Prescaler 5.2 Using Timer0 with an External Clock 5.3 Prescaler Register 5-1: OPTION_REG Register TABLE 5-1: Registers Associated with Timer0 6.0 Timer1 Module Register 6-1: T1CON: Timer1 Control Register (Address: 10h) 6.1 Timer1 Operation in Timer Mode 6.2 Timer1 Counter Operation FIGURE 6-1: Timer1 Incrementing Edge 6.3 Timer1 Operation in Synchronized Counter Mode FIGURE 6-2: Timer1 Block Diagram 6.4 Timer1 Operation in Asynchronous Counter Mode 6.4.1 Reading and writing Timer1 in asynchronous counter mode 6.5 Timer1 Oscillator TABLE 6-1: Capacitor Selection for the Timer1 Oscillator 6.6 Resetting Timer1 Using a CCP Trigger Output 6.7 Resetting of Timer1 Register Pair (TMR1H, TMR1L) 6.8 Timer1 Prescaler TABLE 6-2: Registers Associated with Timer1 as a Timer/Counter 7.0 Timer2 Module FIGURE 7-1: Timer2 Block Diagram Register 7-1: T2CON: Timer2 Control Register (Address 12h) 7.1 Timer2 Prescaler and Postscaler 7.2 Output of TMR2 TABLE 7-1: Registers Associated with Timer2 as a Timer/Counter 8.0 Capture/Compare/PWM Modules 8.1 CCP1 Module TABLE 8-1: CCP Mode - Timer ResourceS REQUIRED Register 8-1: CCP1CON Register Register (Address: 17h/1DH) 8.2 Capture Mode 8.2.1 CCP pin Configuration FIGURE 8-1: Capture Mode Operation Block Diagram 8.2.2 Timer1 Mode Selection 8.2.3 Software Interrupt 8.2.4 CCP Prescaler EXAMPLE 8-1: Changing between capture prescalers 8.3 Compare Mode FIGURE 8-2: Compare Mode Operation Block Diagram 8.3.1 CCP Pin Configuration 8.3.2 timer1 Mode Selection 8.3.3 Software Interrupt Mode 8.3.4 Special Event Trigger 8.4 PWM Mode (PWM) FIGURE 8-3: Simplified PWM Block Diagram FIGURE 8-4: PWM Output 8.4.1 PWM period 8.4.2 PWM Duty Cycle 8.4.3 SetUp for PWM Operation TABLE 8-2: Example PWM Frequencies and Resolutions at 20 MHz TABLE 8-3: Registers Associated with Capture, compare, and Timer1 TABLE 8-4: Registers Associated with PWM and Timer2 9.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART) Register 9-1: TXSTA: Transmit Status and Control Register (Address: 98h) Register 9-2: RCSTA: Receive Status and Control Register (Address 18h) 9.1 USART Baud Rate Generator (BRG) 9.1.1 SAMPLING TABLE 9-1: Baud Rate Formula TABLE 9-2: Registers Associated with Baud Rate Generator TABLE 9-3: Baud Rates for Asynchronous Mode (BRGH = 0) TABLE 9-4: Baud Rates for Asynchronous Mode (BRGH = 1) 9.2 USART Asynchronous Mode 9.2.1 USART Asynchronous Transmitter FIGURE 9-1: USART Transmit Block Diagram FIGURE 9-2: Asynchronous Master Transmission FIGURE 9-3: Asynchronous Master Transmission (Back to Back) TABLE 9-5: Registers Associated with Asynchronous Transmission 9.2.2 USART Asynchronous Receiver FIGURE 9-4: USART Receive Block Diagram FIGURE 9-5: Asynchronous Reception TABLE 9-6: Registers Associated with Asynchronous Reception 9.2.3 Setting up 9-bit mode with Address Detect FIGURE 9-6: USART Receive Block Diagram FIGURE 9-7: Asynchronous Reception with Address Detect FIGURE 9-8: Asynchronous Reception with Address Byte First TABLE 9-7: Registers Associated with Asynchronous Reception 9.3 USART Synchronous Master Mode 9.3.1 USART Synchronous Master Transmission TABLE 9-8: Registers Associated with Synchronous Master Transmission FIGURE 9-9: Synchronous Transmission FIGURE 9-10: Synchronous Transmission (Through TXEN) 9.3.2 USART Synchronous Master Reception TABLE 9-9: Registers Associated with Synchronous Master Reception FIGURE 9-11: Synchronous Reception (Master Mode, SREN) 9.4 USART Synchronous Slave Mode 9.4.1 USART Synchronous Slave Transmit TABLE 9-10: Registers Associated with Synchronous Slave Transmission 9.4.2 USART Synchronous Slave Reception TABLE 9-11: Registers Associated with Synchronous Slave Reception 10.0 Analog-to-Digital (A/D) Converter Module Register 10-1: ADCON0 Register (Address: 1Fh) Register 10-2: ADCON1 Register (Address: 9Fh) FIGURE 10-1: A/D Block Diagram 10.1 A/D Acquisition Requirements EQUATION 10-1: Acquisition Time FIGURE 10-2: Analog Input Model 10.2 Selecting the A/D Conversion Clock TABLE 10-1: Tad vs. Maximum Device Operating Frequencies (Standard devices (C)) 10.3 Configuring Analog Port Pins 10.4 A/D Conversions FIGURE 10-3: A/D Conversion Tad Cycles 10.4.1 A/D Result Registers FIGURE 10-4: A/D Result Justification 10.5 A/D Operation During SLEEP 10.6 Effects of a RESET TABLE 10-2: Registers/bits Associated with A/D 11.0 Special Features of the CPU 11.1 Configuration Bits Register 11-1: Configuration Word (ADDRESS 2007H)(1) 11.2 Oscillator Configurations 11.2.1 Oscillator Types 11.2.2 Crystal Oscillator/CERAmic Resonators FIGURE 11-1: Crystal/Ceramic Resonator Operation (HS, XT or LP OSC Configuration) FIGURE 11-2: External Clock Input Operation (HS, XT or LP OSC Configuration) TABLE 11-1: Ceramic Resonators TABLE 11-2: Capacitor Selection for Crystal Oscillator 11.2.3 RC Oscillator FIGURE 11-3: RC Oscillator Mode 11.3 RESET FIGURE 11-4: Simplified Block Diagram of On-chip Reset Circuit 11.4 Power-on Reset (POR) 11.5 Power-up Timer (PWRT) 11.6 Oscillator Start-up Timer (OST) 11.7 Brown-out Reset (BOR) 11.8 Time-out Sequence 11.9 Power Control/Status Register (PCON) TABLE 11-3: Time-out in Various Situations TABLE 11-4: Status Bits and Their Significance TABLE 11-5: Reset Condition for Special Registers TABLE 11-6: Initialization Conditions for all Registers FIGURE 11-5: Time-out Sequence on Power-up (MCLR Tied to Vdd) FIGURE 11-6: Time-out Sequence on Power-up (MCLR not Tied to Vdd): Case 1 FIGURE 11-7: Time-out Sequence on Power-up (MCLR not Tied to Vdd): Case 2 FIGURE 11-8: Slow Rise Time (MCLR Tied to Vdd) 11.10 Interrupts FIGURE 11-9: Interrupt Logic 11.10.1 INT Interrupt 11.10.2 TMR0 Interrupt 11.10.3 PortB INTCON CHANGE 11.11 Context Saving During Interrupts EXAMPLE 11-1: Saving STATUS, W, and PCLATH Registers in RAM 11.12 Watchdog Timer (WDT) FIGURE 11-10: Watchdog Timer Block Diagram TABLE 11-7: Summary of Watchdog Timer Registers 11.13 Power-down Mode (SLEEP) 11.13.1 Wake-up from SLEEP 11.13.2 Wake-Up Using Interrupts FIGURE 11-11: Wake-up from Sleep Through Interrupt 11.14 In-Circuit Debugger TABLE 11-8: Debugger Resources 11.15 Program Verification/Code Protection 11.16 ID Locations 11.17 In-Circuit Serial Programming 11.18 Low Voltage ICSP Programming 12.0 Instruction Set Summary TABLE 12-1: Opcode Field Descriptions FIGURE 12-1: General Format for Instructions TABLE 12-2: PIC16F870/871 Instruction Set 12.1 Instruction Descriptions 13.0 Development Support 13.1 MPLAB Integrated Development Environment Software 13.2 MPASM Assembler 13.3 MPLAB C17 and MPLAB C18 C Compilers 13.4 MPLINK Object Linker/ MPLIB Object Librarian 13.5 MPLAB C30 C Compiler 13.6 MPLAB ASM30 Assembler, Linker, and Librarian 13.7 MPLAB SIM Software Simulator 13.8 MPLAB SIM30 Software Simulator 13.9 MPLAB ICE 2000 High Performance Universal In-Circuit Emulator 13.10 MPLAB ICE 4000 High Performance Universal In-Circuit Emulator 13.11 MPLAB ICD 2 In-Circuit Debugger 13.12 PRO MATE II Universal Device Programmer 13.13 PICSTART Plus Development Programmer 13.14 PICDEM 1 PIC MCU Demonstration Board 13.15 PICDEM.net Internet/Ethernet Demonstration Board 13.16 PICDEM 2 Plus Demonstration Board 13.17 PICDEM 3 PIC16C92X Demonstration Board 13.18 PICDEM 4 8/14/18-Pin Demonstration Board 13.19 PICDEM 17 Demonstration Board 13.20 PICDEM 18R PIC18C601/801 Demonstration Board 13.21 PICDEM LIN PIC16C43X Demonstration Board 13.22 PICkitTM 1 FLASH Starter Kit 13.23 PICDEM USB PIC16C7X5 Demonstration Board 13.24 Evaluation and Programming Tools 14.0 Electrical Characteristics Absolute Maximum Ratings † FIGURE 14-1: PIC16FXXX Voltage-Frequency Graph FIGURE 14-2: PIC16LFXXX Voltage-Frequency Graph 14.1 DC Characteristics: PIC16F870/871 (Industrial, Extended) PIC16LF870/871 (Commercial, Industrial) 14.2 DC Characteristics: PIC16F870/871 (Industrial) 14.3 DC Characteristics: PIC16F870/871 (Extended) 14.4 Timing Parameter Symbology FIGURE 14-3: Load Conditions FIGURE 14-4: External Clock Timing TABLE 14-1: EXTERNAL CLOCK TIMING REQUIREMENTS FIGURE 14-5: CLKO and I/O Timing TABLE 14-2: CLKO and I/O Timing Requirements FIGURE 14-6: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing FIGURE 14-7: Brown-out Reset Timing TABLE 14-3: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer, and brown-out reset Requirements FIGURE 14-8: Timer0 and Timer1 External Clock Timings TABLE 14-4: Timer0 and Timer1 External Clock Requirements FIGURE 14-9: Capture/Compare/PWM Timings (CCP1) TABLE 14-5: Capture/Compare/PWM Requirements (CCP1) FIGURE 14-10: Parallel Slave Port Timing (PIC16F871 only) TABLE 14-6: Parallel Slave Port Requirements (PIC16f871 only) FIGURE 14-11: USART Synchronous Transmission (Master/Slave) Timing TABLE 14-7: USART Synchronous Transmission Requirements FIGURE 14-12: USART Synchronous Receive (Master/Slave) Timing TABLE 14-8: USART Synchronous Receive Requirements TABLE 14-9: PIC16F870/871 (Industrial) PIC16LF870/871 (Industrial) FIGURE 14-13: A/D Conversion Timing TABLE 14-10: A/D Conversion Requirements 15.0 DC and AC Characteristics Graphs and Tables FIGURE 15-1: Typical Idd vs. Fosc OVER Vdd (HS Mode) FIGURE 15-2: Maximum Idd vs. Fosc OVER Vdd (HS Mode) FIGURE 15-3: Typical Idd vs. Fosc OVER Vdd (XT Mode) FIGURE 15-4: Maximum Idd vs. Fosc OVER Vdd (LP Mode) FIGURE 15-5: Typical Idd vs. Fosc OVER Vdd (LP Mode) FIGURE 15-6: Maximum Idd vs. Fosc OVER Vdd (XT Mode) FIGURE 15-7: Average Fosc vs. Vdd for Various Values of R (RC Mode, C = 20 pF, 25°C) FIGURE 15-8: Average Fosc vs. Vdd for Various Values of R (RC Mode, C = 100 pF, 25°C) FIGURE 15-9: Average Fosc vs. Vdd for Various Values of R (RC Mode, C = 300 pF, 25°C) FIGURE 15-10: Ipd vs. Vdd (Sleep Mode, all peripherals disabled) FIGURE 15-11: DIbor vs. Vdd over Temperature FIGURE 15-12: TYPICAL AND MAXIMUM DItmr1 vs. Vdd over Temperature (-10°C TO 70°C, Timer1 with Oscillator, XTAL=32 kHz, C1 and C2=50 pF) FIGURE 15-13: TYPICAL AND MAXIMUM DIwdt vs. Vdd over Temperature FIGURE 15-14: Typical, Minimum and Maximum WDT Period vs. Vdd (-40°C to 125°C) FIGURE 15-15: Average WDT Period vs. Vdd over Temperature (-40°C to 125°C) FIGURE 15-16: Typical, Minimum and Maximum Voh vs. Ioh (Vdd = 5V, -40°C to 125°C) FIGURE 15-17: Typical, Minimum and Maximum Voh vs. Ioh (Vdd = 3V, -40°C to 125°C) FIGURE 15-18: Typical, Minimum and Maximum Vol vs. Iol (Vdd = 5V, -40°C to 125°C) FIGURE 15-19: Typical, Minimum and Maximum Vol vs. Iol (Vdd = 3V, -40°C to 125°C) FIGURE 15-20: Minimum and Maximum Vin vs. Vdd, (TTL Input, -40°C to 125°C) FIGURE 15-21: Minimum and Maximum Vin vs. Vdd (ST Input, -40°C to 125°C) FIGURE 15-22: Minimum and Maximum Vin vs. Vdd (I2C Input, -40°C to 125°C) 16.0 Packaging Information 16.1 Package Marking Information Package Marking Information (Cont’d) 28-Lead Skinny Plastic Dual In-line (SP) – 300 mil (PDIP) 28-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC) 28-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP) 40-Lead Plastic Dual In-line (P) – 600 mil (PDIP) 44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP) 44-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC) Appendix A: Revision History Revision A (December 1999) Revision B (April 2003) Revision C (January 2013) Appendix B: Device Differences TABLE B-1: Device Differences Appendix C: Conversion Considerations Appendix D: Migration from Mid-range to Enhanced Devices Appendix E: Migration from High-end to Enhanced Devices INDEX The Microchip Web Site Customer Change Notification Service Customer Support Reader Response PIC16F870/871 Product Identification System Sales and Support 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